THE decrease of minimum feature sizes in deep submicron and nanoscale IC technologies has been accompanied by a proportional decrease in interconnect cross-sectional area and pitch. Increasing interconnect density, scaling of supply voltage and faster clock rates have resulted in increased parasitic resistance, capacitance, and inductance for on-chip interconnects. These interconnect parasitic elements have begun influencing the circuit and system performances in terms of large propagation delay and high power consumption. In fact, more than 50% of the total dynamic power is dissipated in interconnects in current processors, and this is expected to rise to 65%–80% over the next several years [1]. Global interconnect delay is increasing at a very high rate even though gate delay and lower level metal interconnect delay are decreasing.

On-chip interconnects also suffer from various DSM noise sources like power-grid fluctuations, electromagnetic noise, and alpha-particle radiation. Manufacturing defects also cause unavoidable errors in the systems. These induced errors create serious data transmission reliability concerns for interconnects. Therefore, error-correction scheme is required for on-chip interconnects [3].

Crosstalk noise due to parasitic capacitance is dominant at low clock frequency, and interconnect usually modeled as *RC* netlist for timing and noise prediction in design automation tools [4]. With the increase of operating frequency in GHz range, the parasitic inductive impedance (ω *L*) becomes comparable with the line resistance and the transition time of the incident signals are comparable to the time of flight. As a result, wire inductance is becoming increasingly significant; and it affects the interconnect performance in many ways [5]. Wire delay is high for certain switching patterns in an inductance-dominant bus. The switching noise is caused by the changes in current through various parasitic inductances. Simultaneous switching of I/O drivers and internal circuits lead to increased voltage drop on the power supply lines. As a result, noise is induced in the supply and ground voltages in the presence of large current. This is known as ground bounce noise [5]. Additionally, the long range effect of the inductive crosstalk causes serious signal integrity-related problems [6].

There have been many techniques introduced to counteract the deleterious effects of inductive crosstalk. These techniques are implemented on the packages and modules for off-chip interconnect. For low frequency voltage drop, the on-chip decoupling capacitor is an effective way to reduce inductive crosstalk. Other techniques involve controlling the arrival time of the clock signal or retiming the sequential circuits [6]. All these techniques are technology and implementation dependent.

Coding techniques provide a technology- and implementation-independent solution to DSM interconnect constraints. They also offer a common framework for jointly solving delay, power, and reliability issues [7]. This paper proposes a coding scheme which will provide both inductive crosstalk avoidance and error-correction scheme for coupled *RLC* interconnects.

The rest of the paper is organized as follows. Section II presents related work on bus-encoding techniques for capacitive- and inductive-crosstalk avoidance and error-correction coding for on-chip interconnects. Section III describes the parasitic inductive effect for on-chip interconnects and worst case switching pattern for both *RC* and *RLC* lines. In Section IV, general scheme for fault-tolerant busses and some basic properties of error-correcting codes are presented. Section V discusses *RLC* coupling aware encoding techniques. This section also presents a comparison among various unified crosstalk avoidance and error-correction coding schemes in terms of area overhead. Section VI summarizes and concludes the paper.

The role of different schemes for power, delay and DSM noise reduction has been investigated previously. Shield insertion [8], duplicate message bits (DAP) [9], and repeater insertion [10] are various hardware based approach to prevent crosstalk and interference. In recent years, coding technique has emerged as a solution to on-chip power, delay and DSM noise problems in global interconnects. A number of low-power dynamic bus encoding schemes have been proposed, such as, bus-invert (BI) [11] and partial bus invert (PBI) [12]. These codes are appropriate for uncorrelated data patterns, i.e., for patterns randomly distributed both in time and space. These coding schemes are aimed at reducing the switching activities for low power, are efficient for off-chip buses where node self-capacitance is several times larger than the coupling capacitance with negligible parasitic on-chip inductance. But, for on-chip buses, inter-wire coupling capacitance is the major source of delay and energy consumption. Odd/even BI (OEBI) [13] and coupling driven bus invert (CBI) [14] attempt to reduce coupling energy and delay by lowering the average value of both the self- and coupling transitions. Transition pattern coding (TPC) is another technique for reducing delay due to capacitive coupling [15]. But, TPC requires a very complex encoder and decoder. Boundary shift coding was first explored in [16] for capacitive coupling and error-correction for DSM buses. In [7], a unified coding framework for system-on-chip (SoC) networks has been explored. Further, a bus encoding method based on the codeword selection for crosstalk avoidance and error-correction is proposed in [17].

Most of the previous bus encoding techniques is related to capacitive crosstalk reduction. Capacitive crosstalk aware encoding schemes will not be useful for inductance dominant interconnects as their characteristics are different and in some respect are quite opposite A technique based on BI coding has been proposed in [18], [19] for inductive crosstalk minimization. Bus encoding techniques based on time and space redundancy to reduce delay, power and simultaneous switching noise in *RLC* interconnects were proposed in [20]. But, these coding schemes do not provide ECC and require significant decoding resources. Some hybrid BI coding schemes like odd-even BI (OEBI), partial BI (PBI) and odd-even-partial BI (OEPBI) for simultaneous switching noise reduction and DSM error-correction for inductive dominant buses have been proposed in [21]. These coding techniques employ linear error control coding and need additional wires to transmit parity bits.

In this paper, a modified boundary shift coding is proposed for treating both inductive crosstalk and DSM noise. Unlike [7], [20], [21] where hamming error-correction coding are used, this boundary shift coding employ simple parity bits schemes which results in a much simpler encoder and decoder circuits and it also requires fewer number of additional wires in on-chip interconnects. Besides, various other joint coding schemes for *RLC* interconnects are proposed and compared in terms of required code rates.

SECTION III

## Crosstalk Noise in DSM Bus

In this paper, DSM bus is modeled as a sequence of parallel, minimum width, identically-dimensioned, coplanar wires with two shielded lines at both ends. It is also assumed that bus retains a previously-transmitted value until the next one is transmitted. All drivers and receivers are of uniform size, and all signal wires have uniform width, spacing, and length. It has been further assumed that synchronous latches located at the transmitter side make all the bus lines switch at the same time.

Crosstalk noise results from the undesirable coupling of energy from a switching line (aggressor) to a passive line (victim). It causes delay faults, logical malfunctions, and energy consumption in on-chip interconnects. There are two types of crosstalk; capacitive and inductive coupling.

In DSM era, the coupling capacitance is significant compared to metal-to-ground capacitance. Therefore, nearest neighboring lines experience majority of charge excited by an aggressor and further neighboring lines contribute minimally to the capacitive coupling. Hence, capacitance coupling is considered as a *short range* effect [10]. Due to this short range effect of the capacitive coupling delay of a line depends on the transitions on the line and its adjacent lines. Table I lists the delay of the line *l* of an n-bit bus, where 1 < *l* < *n*, for certain combinations of transitions. Here, ↑ indicates a 0-to-1 transition, ↓ indicates a 1-to-0 transition, “-” indicates no transition on the line and λ is the ration of coupling capacitance to the bulk capacitance. It is seen in Table I that the worst case delay can be significantly higher than the delay in the absence of coupling and the opposite switching pattern of the first neighbors to the victim line creates the worst case delay. This is due to the fact that when two lines switch in opposite directions, the effective coupling capacitance between them is largest [23].

In an inductive-coupled line, coupling excites an induced current that needs to find a return path in order to form a current loop. But, due to the presence of the receiver's gate capacitance, loaded at the end of the wire, there is no dc path for the return current directly back to ground. In this case, the orthogonal layer cannot acts as the ground plane since mutual inductance between two lines is zero for two orthogonal lines. In this case, all higher order neighbors are considered as mutual inductance decays slowly with increasing spacing. Therefore, inductive coupling is considered as a *long range* issue [24].

Worst case switching patterns for an *RLC* line have been investigated in [18], [19]. In an *RLC* line when all neighboring lines simultaneously switch in the same direction as the victim line does, a current of different direction to that of victim line currents generates. As a result, delay and noise on the victim line is higher than the case where the signals switch in the same direction. Worst case switching pattern for a 3-bit bus changes to ↑↑↑ in an inductive-coupling dominant interconnect in contrast to ↑↓↑ in a capacitive-dominant interconnect for a 3-bit bus. No closed form delay expression like those of *RC* lines in Table I is available for *RLC* lines due to the long range inductive coupling. But it could be intuitively derived that ↑↑↑ will impose higher delay compared to ↑↑↓ as number of simultaneous switching count is higher for the former case. On the contrary, worst case switching pattern of a coupling *RLC* line is the best case pattern of a coupling *RC* line.

SECTION IV

## Fault Tolerant Buses

DSM buses suffer from various sources of noise such as power grid fluctuation, crosstalk from other interconnect, electromagnetic interference etc. An approximate characterization of the error phenomenon has been proposed in [25]. According to this approximation, it is assumed that a Gaussian distributed noise voltage *V*_{N} with variance σ^{2} is added to the signal waveform to represent the cumulative effect of all the noise sources. The probability of bit error is given by [26]
TeX Source
$$\varepsilon = Q \left({V_{dd}\over 2\sigma_N}\right)\eqno{\hbox{(1)}}$$where *Q*(*z*) is defined as the probability that a Gaussian random variable *x* with mean zero and variance one exceeds the value *z*.

The reliability issues are addressed by ECC. ECC was proposed in [25] to achieve energy efficiency for on-chip buses. ECC involves mapping *k* data bits to be transmitted on the bus to *n* code bits resulting in an (*n*,*k*) code having a code rate of *k*/*n*. So, ECC encoder adds *m* or *n*−*k* extra parity/check bits in order to obtain codewords belonging to a codespace with a minimum Hamming distance. Error control is possible if the Hamming distance between any two codewords is greater than one. Hamming coding provides a linear and systematic ECCs as a few redundant bits are appended to the input to generate the codewords [27].

SECTION V

## Joint Crosstalk and ECC for RLC Lines

Various inductive crosstalk avoidance code (CAC) can be combined with ECC to form a unified coding approach to minimize delay and DSM noise in interconnects. Inductive crosstalk avoidance codes like BI, OEBI, PBI and OEPBI involve nonlinear and disruptive mapping from data bits to codewords. So, in a joint coding framework, these codes need to be the outermost code in the framework and linear ECC like Hamming codes follow CAC. Since Hamming codes are systematic, it will generate some parity bits which are appended to crosstalk avoidance codewords. These additional parity bits need to be encoded again for crosstalk avoidance and a linear crosstalk avoidance coding is used for this purpose. Fig. 1 illustrates a joint coding framework for an on-chip *RLC* coupled interconnects.

Shield insertion offers an effective linear crosstalk avoidance codes. It reduces signal delay uncertainty in a coupled *RLC* interconnect. Fig. 2 shows three cases of shield insertion using one, two and three ground lines, respectively. The three-shield interconnect structure exhibits the lowest crosstalk noise among above three structures [28].

In a joint coding approach like above, a greater silicon area is required as both non-linear and linear CACs and systematic ECC are employed. Table II lists number of wires required for various unified CAC and ECC for a 16-bit data buses.

As shown in the above table, coderate decreases to very low value in a joint coding framework. Boundary shift code for capacitive crosstalk avoidance proposed in [16] can be modified for an inductance-dominant on-chip interconnects. As worst case delay occurs in an *RLC* interconnect when all neighboring lines simultaneously switch in the same direction as the victim line does, a pair of codewords would contain an invalid transition if transition from one codeword to the other causes adjacent bits to switch in the same directions. We would define a *dependent boundary* in a word as a place where two adjacent bits are the same and it will be denoted by the leftmost bit of the boundary. For the following two codewords *C*_{1} → 1011 and *C*_{1} → 0111 have dependent boundaries {3] and {2,3}. Since it has an overlap in dependent boundaries, transition will create delay in an *RLC* interconnect. In boundary shift coding, 1-bit circular right shift of a codeword with even boundaries yields a new codeword with no even dependent boundaries. This property is utilized in generating error-correcting codes with no odd dependent boundaries. If *c* is an [*n*,*k*,*d*] then duplicating each bit position will yield a code *C*′ with an [2*n*,*k*,2*d*] code with no odd boundaries. Now, a shifted version of *C*′ will have no common dependent boundaries with *C*. Therefore, in order to avoid simultaneous switching between two consecutive codewords we will alternate between *C* and *C*′. Usually, codewords is right shifted during odd clock cycle and is kept as it is during even clock cycle.

In order to add ECC feature to the CAC code, a single-even-parity-check code is used in the codeword in stead of a Hamming code. For a *k* bit data buses, a single parity would generate a [*k*+1,*k*,2] codeword and then, duplicating and shifting will generate a [2*k*+1,*k*,3] single-error-correcting code [16].

Figs. 3 and 4 shows encoder and decoder structure of the modified boundary shift coding for crosstalk avoidance in an inductance-dominant on-chip interconnect. Encoder block duplicates, shift and adds parity to a 4-bit data {*x*_{0} *x*_{1} *x*_{2} *x*_{3}} and generate a 9-bit wide codeword {*y*_{0} *y*_{1} *y*_{2} *y*_{3} *y*_{4} *y*_{5} *y*_{6} *y*_{7} *y*_{8}}. At the decoder side, left shift is done on the codeword during odd clock cycles. Since, a duplicate copy of single data bit is transmitted along with even parity code; majority voter logic is employed to yield original information bits. As the distance between two codewords is three here, two errors can be detected and one error can be corrected.

As shown in Fig. 3, 9 wires are required for encoding for a 4-bit data bus. These can be generalized in a straightforward way for larger data buses. Generally, an *n*-bit data bus requires 2*n*+1 number of wires for this boundary shift coding. So, 33 wires are used in encoding a 16-bit data bus which is almost 50% and 41.5% lower than two effective joint CAC and ECC codes namely *BI+Hamming+three-groundline-shielding* and *BI+Hamming+two-groundline-shielding*, respectively. Beside, modified boundary shift coding can eliminate the crosstalk noise completely whereas *BI+Hamming+two-groundline-shielding* provide only partial crosstalk avoidance. This unified coding scheme also requires a simpler encoder and decoder circuitry compared to other joint coding approach for an inductance-dominant interconnect.

SECTION VI

## Summary and Conclusion

On-chip inductive coupling has become a major issue with increasing clock speed, larger die sizes, and the introduction of copper wiring for high-speed interconnects. This will get worse in future technologies due to the increasing gap between gate delay and interconnect delay. This paper presents a modified boundary shift coding for both crosstalk avoidance and error-correction for on-chip *RLC* interconnect. This joint coding framework imposes a comparatively lower wiring overhead on the system along with an easier encoder-decoder circuitry. This coding scheme can be extended further to address low-power issue which reduces self-transition activity in on-chip data buses. Beside, multiple error correction coding scheme can be incorporated by adding more parity bits to the information bits and this will be useful for high-speed energy-efficient reliable on-chip communication.