Various III-V compound heterostructures, such as AlGaAs/InGaAs or InGaAs/InAlAs systems, can be used to create a 2DEG layer with very high electron mobilities. In 2DEG structures with dimensions smaller than the electron mean free path le, electrons can travel without any scattering events. This is referred to as ballistic transport and can be observed even at room temperature over small distances; an excellent overview of ballistic transport is presented in . One-dimensional electron gas transistor channels are used to create high-electron mobility transistors (HEMTs) , which can exhibit up to THz performance.
A. Ballistic T-Branch Junction (TBJ) Devices
TBJs are three-terminal devices patterned in a 2DEG . An SEM image of a TBJ is shown in Fig. 2. TBJs exhibit a nonlinear input-output transfer function  with efficiency characterized by a ballisticity factor α/α0, where α0 = e/2μF at T = 0 K and μF is the Fermi energy of the 2DEG .
We recently studied TBJs in a 2DEG InGaAs/InAlAs heterostructure by varying the device channel length L and operating temperature T . Fig. 3 summarizes the experimental results in terms of α/α0, which increases with decreasing T and decreases as the L/le ratio increases. Another interesting feature is that α/α0 saturates at a nonzero value when L ≫ le; thus, the nonlinear ballistic effect is still observable even for long TBJs at high temperatures. The robustness of the TBJ's nonlinear response is a unique advantage in terms of realizing room-temperature circuits.
B. Ballistic Deflection Transistors
The BDT  is a six-terminal coplanar structure etched into a 2DEG. The dimensions and materials allow electrons to travel quasi-ballistically at room temperature, guided by the central deflector and lateral gate potentials as shown in Fig. 4. The steering voltage is much smaller than that required for gate pinch-off. This low voltage, combined with the low capacitance of the 2DEG features, results in an estimated fT in the THz range . An SEM of a BDT is shown in Fig. 5.
The room temperature measured response of the BDT across a range of differential gate voltages is shown in Fig. 6. The x-axis is the left gate voltage. The asymmetry between the left and right outputs is caused by process variation and slight unevenness in contact placement. A positive left gate and negative right gate voltage results in current gain through the left output branch; current gain is seen through the right output branch when the voltages are reversed. The overlapping response in Fig. 6 is a result of electrons being scattered into the incorrect output. Electron scattering into the pull-up channel accounts for less than 10% of the total current. Gate leakage, where electrons tunnel under the minimum width etching between the gate and channel, accounts for 20% of the total current. These leakage values will decrease as geometries and fabrication techniques are further refined.
One of the major challenges of creating logic with BDTs is the method of converting the output current of one device into the gate voltage of the next device. In the BDT, accumulated gate charge is not dissipated by switching the driving gate input; instead, the lack of driving current creates a high resistance path to VDD and ground through the driving device. One solution is to use a string of resistors between VDD and VSS, shown outside the dashed box in Fig. 7. The output current from the BDT affects the voltage division between VDD and VSS, and the node Vout can then be applied to the next gate. More electrons on a node results in a lower voltage; thus, a flow of electrons represents logic ‘0’.
The empirical model in Fig. 7 uses two voltage-controlled current sources (VCCS) to recreate the output behavior from Fig. 4, with a leakage path between ground and the supply voltage represented by a resistor. To simplify the model, output symmetry is forced by inverting the right channel response about 0 V to create the left channel response.
The 2-input NAND gate can be used to construct any arbitrarily complex logic function. It is thus of immense importance for novel devices to achieve this function if they are to be used for general purpose computation. The NAND gate design shown in Fig. 8 functions as follows: the source is shown as the arrow entering the bottom channel of the left-hand BDT. The differential gate input A guides electrons into the channel labeled A = 1 when gate A is high and gate Ā is low, and into channel A = 0 in the opposite case. The differential gate input B guides electrons in the central region to the channels labeled B = 0 or B = 1 similar to gate A. This results in a flow of electrons (representing a ‘0’) at the output F only when A and B are high. For each other input combination, electrons are driven either to the left output channel or the top right output channel. This behavior results in the logic function A NAND B. To maintain the differential output required to drive the next stage of gates, the left output channel and top right output channel must be connected to create the logic function A AND B.
The empirical model in Fig. 9 is similar to Fig. 8, with a current-controlled voltage source (CCVS) allowing the VCCS instances in the right-hand BDT to react to the current exiting the left-hand BDT. This results in the waveform in Fig. 10, with the outputs delayed by 1 ns. As shown, the output vF switches between 0.15 V and −0.15 V, matching the input voltages. The −0.15 V state, logic low, is achieved only when both inputs are ‘1’. When both inputs are ‘0’, the 0.15 V state is reached. For the ‘01’ and ‘10’ cases, a slightly reduced state of 0.1 V is reached. Thus, the model represents a NAND gate.
Additional experiments planned with fabricated BDTs include testing the current-to-voltage converters to cascade devices, testing other Boolean logic gates, and using cross-coupled BDTs to create memory elements.