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  • Abstract

New CMOS Fully Differential Current Conveyor and Its Application in Realizing Sixth Order Complex Filter

A sixth order complex filter based on the usage of a newly proposed fully differential current conveyor (FDCC) is presented in this paper. The FDCC new structure is based on usage of differential difference operational floating amplifier (DDOFA) [1] and floating current source circuits [2]. The block is realized using 0.25 μm CMOS technology under ±1.5 V power supply. PSPICE simulation for the FDCC is done for testing the block. The simulation shows that the FDCC has ±0.5 V input dynamic range, 95 MHz 3-dB frequency at output terminal under 10 KΩ load and 7.21 mW total power dissipation. The FDCC is used to realize first order complex filter with 1 MHz center frequency and second order complex filter at 500 KHz center frequency. Finally; using cascading technique, a sixth order complex filter at 500 KHz center frequency is proposed. The proposed filter is suitable for applications like Bluetooth receivers. All the proposed filter circuits are simulated using ADS simulator.

SECTION I

INTRODUCTION

Receivers that deals with RF signals use either direct conversion technique or low/high intermediate frequency (IF) conversion technique to extract the baseband signal [3]. Direct conversion receivers suffer from flicker noise and DC offset problems which cause significant degradation in the signal-to-noise ratio, while IF conversion receivers are immune to these effects. However; with the use of IF conversion technique the problem of image signal appears; since both the information and image signals are located symmetrically around the carrier frequency in the frequency domain. If the image signal has higher power than the desired information signal then it can be considered as strong interferer that needs to be eliminated. The conventional method used to reject the image signal is the use of image rejection filters before the mixer [3].

Another method for image rejection is by using complex mixing and filtering. This method is used in applications like Bluetooth receivers as presented in [4]. The complex mixing is done by using two mixers with 90° phase shift; which exists in all quadrature demodulators. As for the complex filtering; the theory is not new [5]. A complex filter has asymmetrical frequency response around j ω axis and thus its time domain response is complex and that's the origin of the complex name. The frequency response of the complex filter is similar to a frequency shifted real time lowpass filter.

Complex filters are implemented using the same circuits used for real time filters like passive RC and active RC circuits. Passive RC complex filters can achieve high image rejection ratio but they show limited selectivity; thus they suffer from adjacent channel interference [4]; while active RC complex filters achieve high image rejection ratio and high adjacent channel interference rejection ratio.

In this paper a new CMOS fully differential current conveyor (FDCC) is proposed and used to realize sixth order active RC complex filter. The paper is organized as follows: Section II describes in details the proposed CMOS realization of the FDCC, Section III review the theory of complex filters presenting a proposed realization for FDCC based first order complex filter, Section IV presents a proposed second order FDCC based complex filter using real time Tow-Thomas filter, Section V discusses the realization of a sixth order complex filter using cascading technique and finally the conclusion in Section VI.

SECTION II

PROPOSED CMOS REALIZATION FOR FDCC

FDCC is a current mode active block that can be used to realize different analog signal processing applications [6]. The circuit symbol of FDCC is presented in Fig. 1(a). The FDCC can be considered a differential version of the current conveyor. The Y terminals are a high impedance port while the X terminals have considerably lower impedance than Y terminals. The Z terminals have large impedance to make the block suitable for current mode applications. The differential voltage applied to the Y port is conveyed to the X port (VYd = VXd) and the X port differential current is conveyed to the Z port (IX1−IX2 = IZ1−IZ2).

Figure 1
Fig. 1. Circuit Symbol (a) FDCC (b) DDOFA.

In this paper; the proposed FDCC structure is based on using differential difference operational floating amplifier (DDOFA) [1], [7] and a floating current source circuit [2]. The DDOFA circuit symbol is presented in Fig. 1(b). The DDOFA structure is divided into three stages: the input stage, gain stage and output stage. The two balanced output currents of the DDOFA are given as follows:Formula TeX Source $${\rm I}_{\rm o+} = -{\rm I}_{\rm o-} = {\rm G}{\rm o}[({\rm V}_1 - {\rm V}_2)-({\rm V}_3 - {\rm V}_4)]\eqno{\hbox{(1)}}$$Where Go is the open loop transconductance gain of the block. Using negative feedback techniques the two differential difference voltages of the DDOFA are equated as follows:Formula TeX Source $${\rm V}_1 - {\rm V}_2 = {\rm V}_3 - {\rm V}_4\quad {\rm G}_{\rm o} \to \infty\eqno{\hbox{(2)}}$$

The CMOS realization of FDCC is shown in Fig. 2. The input stage is formed from two linearized differential amplifiers M1–M20; the linearization technique used depends on forcing the common source node voltage to track the common mode voltage of the input signals [8], [9]. Thus two common mode estimator circuits as the one presented in [9] are used to generate Vcm1 and Vcm2 for the two differential amplifiers. The gain stage is based on cascode amplifier formed with transistors M23–M34. And finally two floating current source circuits formed from M35–M46 [2].

Figure 2
Fig. 2. CMOS realization of the proposed FDCC.

Since the FDCC basic operation is to convey the differential voltage from the Y port to the X port; a DDOFA with negative feedback connection can be used to realize this action between its differential inputs. But since this feedback action is done using the two output currents of the DDOFA output stage; another floating current source circuit is added to the DDOFA basic structure to provide a replica of the DDOFA output currents. The currents of the new output stage are the same as the X port currents.

Thus these new output currents can be considered as the Z port of the FDCC and consequently a complete FDCC is realized. PSPICE simulation for the circuit is done using 0.25 μm model with supply voltage of ±1.5 V. DC analysis is performed to verify the following action of the X port differential voltage to that of Y port with 25 KΩ load at X and Z ports as shown in Fig. 3; the block has ±0.5 V dynamic range. To show the differential current conveying from X to Z terminals; DC analysis is performed for the FDCC with port Y connected to the ground and the Z port load is short circuit; the current following action is achieved over ±1 mA range as shown in Fig. 4. The total power dissipation of the FDCC is 7.21 mW, the 3-dB frequency under 10 KΩ at X and Z terminals is 84 MHz and 95 MHz at X and Z respectively. The input referred noise density is 438 nV/√Hz under 1 KΩ load at X and Z terminals.

Figure 3
Fig. 3. FDCC differential voltage of X port vs. Y port.
Figure 4
Fig. 4. FDCC differential current of Z port vs. X port.
SECTION III

COMPLEX FILTERS THEORY AND STRUCTURE

To understand the principle of complex filters; assume that we have two signals present at the input of an IF superheterodyne receiver; the desired signal is centered at fLo+fC and the image signal at fLo−fC; where fLo is the carrier frequency and fC is the intermediate frequency used. These RF signals are mixed with two local oscillators with 90° phase difference between them. The resultant signals after illuminating the double local oscillator frequency component are the desired signal and image signal located at fC and −fC respectively.

The resultant from the mixing process consists of inphase (I) and quadrature (Q) components. The complex filter is able to distinguish between the image and the desired signal by the phase difference between (I) and (Q) components. In order to select the desired signal and reject the image signal the filter used for this purpose must be centered around fC and have asymmetric frequency response around j ω axis; consequently it has a complex time domain response [4].

The required frequency response can be obtained using linear frequency shifting of a real time LPF [5]. The frequency shifting is done by altering every frequency dependent element used in the LPF such that instead of the element being function is S it becomes function in S−jωc. The obtained filter response resembles the bandpass filter response without its negative frequency side [4].

In this section a proposed first order complex filter based on FDCC is presented in Fig. 5. The filter has two inputs and outputs representing the (I) and (Q) components. The filter is composed of two FDCC based lossy integrators. One used for (I) branch and the other for the (Q) branch. Each integrator consists of one FDCC, four grounded resistors and two grounded capacitors. The transfer function of each lossy integrator is given as follows:Formula TeX Source $${\rm T}({\rm S}) ={{1\over {\rm R}_{\rm O}{\rm C}}\over {\rm S}+ {1\over {\rm R}_{\rm LP}{\rm C}}}\eqno{\hbox{(3)}}$$

Figure 5
Fig. 5. FDCC based first order complex filter.

In order to shift the frequency response of this filter to be centered around fC; two FDCCs and four grounded resistors are used to perform this task [4], [5]. Using direct analysis; the filter inphase and quadrature outputs are given as follows:Formula TeX Source $$\eqalignno{{\rm V}_{\rm OI} &= {{1\over {\rm R}_{\rm O}{\rm C}}\over {\rm S}+{1\over {\rm R}_{\rm LP}C}}\left({\rm V}_{\rm inI}-{{\rm R}_{\rm O}\over {\rm R}_{\rm C}}{\rm V}_{\rm OQ}\right)&\hbox{(4)}\cr{\rm V}_{\rm OQ} &= {{1\over {\rm R}_{\rm O}{\rm C}}\over {\rm S}+{1\over {\rm R}_{\rm LP}C}}\left({\rm V}_{\rm inQ}-{{\rm R}_{\rm O}\over {\rm R}_{\rm C}}{\rm V}_{\rm OI}\right) &\hbox{(5)}}$$

The filter center frequency and its 3-dB frequency are defined in the following equation:Formula TeX Source $${\rm f}_{\rm C} = {1\over 2\pi {\rm R}_{\rm C}{\rm C}};\quad {\rm f}_{3{\rm dB}} = {1\over 2\pi {\rm R}_{\rm LP}{\rm C}}+ {\rm f}_{\rm C}\eqno{\hbox{(6)}}$$

The filter is simulated using ADS simulator. For 1 MHz center frequency and 1.4 MHz 3-dB frequency; the values of the passive elements used in the filter are as follows: RC = 3.2 KΩ, Ro = 8 KΩ, RLP = 10 KΩ and C = 50 pF. The filter (I) and (Q) outputs are identical. The (I) output voltage is shown in Fig. 6.

Figure 6
Fig. 6. FDCC based first order complex filter frequency response.
SECTION IV

FDCC BASED SECOND ORDER COMPLEX FILTER

In this section a second order complex filter based on FDCC is proposed. As explained in the last section; any complex filter can be realized using frequency shifting of real time filter [5]. Thus the proposed design uses the same frequency transformation technique. The proposed design of the second order filter is based on the famous Tow-Thomas Biquad filter. The filter consists of two FDCC based integrators and one FDCC based voltage to current converter; in addition to grounded resistors and capacitors as shown in Fig. 7. Using direct analysis the filter transfer function, cutoff frequency, quality factor and DC gain are derived in the following equations:Formula TeX Source $$\eqalignno{{{\rm V}_{\rm LP}\over {\rm V}_{\rm in}} &= {{1\over {\rm R}_2{\rm R}_4{\rm C}_1{\rm C}_2}\over {\rm S}^2 + {\rm S} {1\over {\rm R}_1 {\rm C}_1}{1\over {\rm R}_2{\rm R}_3{\rm C}_1{\rm C}_2}} &\hbox{(7)} \cr{ω}_{\rm LP} &=\sqrt{{1\over {\rm R}_2{\rm R}_3 {\rm C}_1 {\rm C}_2}};\quad{\rm Q} ={\rm R}_1\sqrt{{{\rm C}_1\over {\rm R}_2{\rm R}_3 {\rm C}_2}};\cr{\rm DC\ gain} &={{\rm R}_3\over {\rm R}_4} &\hbox{(8)}}$$

Figure 7
Fig. 7. FDCC based Tow-Thomas real time Filter.

In order to change this filter to become complex; two real time filters are used for the (I) and (Q) components. Each integrator used is shifted in the frequency domain in the same manner shown in Section III. This will require the use of four FDCC based voltage to current converters and eight resistors as seen in Fig. 8.

Figure 8
Fig. 8. Complete second order complex filter block diagram.

The complete filter is simulated using ADS. Using equal R equal C design, the resistors and the capacitors used in the second order complex filter to give center frequency of 500 KHz are as follows RC = 6.3 KΩ and C1 = C2 = 50 pF. The values of the resistors of the Tow-Thomas filter is given as follows R2 = R3 = R4 = 10 KΩ and R1 = 7 KΩ. The simulation result is shown in Fig. 9. The complex filter is used in applications like Bluetooth receivers. This proposed design is very simple comparing to other designs used for the same purpose [4].

Figure 9
Fig. 9. Complete second order complex filter frequency response.
SECTION V

A FDCC BASED SIXTH ORDER COMPLEX FILTER

A sixth order complex filter is presented in this section; the filter implementation is realized using three second order complex filters like the one presented in the last section connected in cascade. The center frequency is set at 500 KHz. The same values of resistors and capacitors are used as in the previous section. The filter is simulated using ADS as well. Simulation result of the filter frequency response is presented in Fig. 10. The filter selectivity has improved significantly with increasing the filter order.

Figure 10
Fig. 10. FDCC based sixth order complex filter frequency response.
SECTION VI

CONCLUSION

A new CMOS realization for a fully differential current conveyor is proposed. The block is designed and simulated using PSPICE with 0.25 μm technology model. The block is used to realize first, second and sixth order complex filter. The center frequency of the proposed first order filter is set at 1 MHz while for the second and sixth order is set at 500 KHz. The proposed filters design is very simple. The filters can be used in communication systems like Bluetooth receivers.

Footnotes

Eman A. Soliman is with the Electrical and Electronics Engineering Department, Faculty of Information Engineering and Technology, German University in Cairo, Cairo, Egypt Email: eman.azab@guc.edu.eg.

Soliman A. Mahmoud is with the Electrical and Electronics Engineering Department, Faculty of Information Engineering and Technology, German University in Cairo, Cairo, Egypt Email: soliman.awad@guc.edu.eg.

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Eman A. Soliman

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Soliman A. Mahmoud

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