Frequency tuning of continuous-time filters is necessary due to fabrication tolerances, temperature and other variations. Automatic on-chip tuning avoids expensive factory trimming by having a dedicated tuning circuitry on the chip. The implementation is often known as Master-Slave automatic frequency tuning, in which either a replica of the main filter or its building block is placed in and continuously tuned by a feedback loop. The replica is called the master and the main filter the slave [1], [2], [3]. Fig. 1 shows a voltage-controlled filter (VCF) as the master; or the VCF can be replaced with a voltage-controlled oscillator (VCO) as the master. In both the VCF and VCO cases, the tuning signal is generated by a phase locked loop (PLL), which is eventually to lock the master filter or VCO to the tuned frequency.

Both the VCF and VCO tuning schemes require a sinusoidal signal source. In the VCF, it is provided externally as an input; whereas in the VCO it is generated by the VCO itself. This can be a disadvantage since it is challenging to generate a good quality sinusoidal source on-chip, whereas the usual clock signal is a square wave.

A sigma-delta modulation (SDM) feedback loop also can be used for the filter tuning. In [4], a continuous-time filter in a sigma-delta modulator is tuned by a digital tuning signal, which is generated by measuring the noise spectral densities of the modulator output digitally during the loop's normal operation. The multi-bit digital tuning signal is adjusted according to the measured spectral densities. Some amount of DSP signal processing is required to generate the multi-bit tuning signal.

Another multi-bit digital tuning technique for a continuous-time filter in a sigma-delta modulator is also reported [5]. A multi-bit tuning code is generated by measuring the variance of the modulator output, which is an indicator of the time constant of the continuous-time loop filter. The measuring of the variance involves multi-bit digital signal processing during the modulator's normal operation.

In this paper, we present a simple 1-bit digital tuning technique by using unstable sigma-delta modulation. The 1-bit digital tuning signal can be generated with simple digital circuitry without any multi-bit digital signal processing. A highly unstable SDM loop with a 3rd-order and a 4th-order loop filter is used as an example, and its asymmetrical tuning response is measured by simulation. Detailed discussion is provided for the asymmetrical nature of the 1-bit tuning technique.

SECTION II

## 1-BIT TUNING BY UNSTABLE SDM

A sigma-delta modulator (SDM) as illustrated in Fig. 2 performs noise-shaping by oversampling the input signal. The sampling is performed either at the input for a discrete-time SDM or at the quantizer for a continuous-time SDM. The noise-shaping is accomplished through a properly designed feedback loop. The SDM is normally designed in stable operation with a fair amount of margin to its unstable region. This includes proper choose of loop order, noise-shaping gain, and quantization level of the SDM. The loop filter also has to be designed and tuned accurately.

However, for filter tuning purpose, a highly unstable SDM can be chosen and designed in such a way that its stability is very sensitive to the tuning of its loop filter. A tuning signal can therefore be generated by detecting the stability of the SDM loop, and the tuning signal can be fed back to tune the filter as in the Master-Slave scheme.

The detection of stability can be simply an amplitude detection circuit such as a peak detector or an envelope detector, requiring no multi-bit digital circuitry or multi-bit signal processing. An unstable SDM loop saturates its quantizer, causing extreme amplitudes or extreme amplitude swings at the output, which can be easily detected. Since the detection involves only two states: stable or unstable, the output can be represented by a 1-bit digital signal, which is fed back as a filter tuning signal.

Fig. 3 illustrates such a tuning scheme. This is a continuous-time SDM loop with the sampling action taking place at the quantizer. The input section of the SDM loop is removed entirely, because an input signal is not necessary for the filter tuning purpose. This corresponds to a zero input scenario and simplifies the circuitry considerably. In this case, a stable state would see an output signal of low-level amplitude, corresponding to the zero input scenario, while an unstable state would yield a signal of extreme amplitude level, depending on the quantizer and detection scheme.

The 1-bit frequency tuning response is asymmetrical as will be shown in Section III and will be discussed with details in Section IV. Because of this, the 1-bit tuning process starts always from unstable state and keeps tuning toward stable state until stability is reached. This can be implemented with a simple digital counter circuit, as shown in Fig. 4. The digital counter will keep counting up for an input that corresponds to the unstable state, while a signal corresponding to the stable state can be used to disable and hold the counter once the filter is tuned and a stable loop is reached. As shown in Fig. 4, the final analog tuning signal is generated by D/A converting the output of the digital counter.

Two critical questions are whether the highly unstable SDM loop is sensitive enough for filter tuning, and how accurate can the tuning be? By simulation on two examples, we show in the following section that the accuracy of the 1-bit digital tuning can be up to 2%.

As an example, a third-order 3-bit continuous-time SDM is chosen, whose noise transfer function (NTF) is (1−*z*^{−1})^{3}. A non-return-to-zero (NRZ) type D/A is used with a digital delay (*z*^{−1}) placed in the feedback path. The loop filter transfer function in discrete form is written as
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$$
H(z) = {3z^3 - 3z^2 +z\over (z-1)^3}\eqno{\hbox{(1)}}$$

The correspondent continuous-time loop filter can be obtained through the pulse invariant transformation [6], [7].
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$$H'(s)= 3+{13/3\over Ts}+{3\over (Ts)^2}+{1\over (Ts)^3}\eqno{\hbox{(2)}}$$where T is the sampling period of the SDM. The continuous-time filter can be implemented with three identical integrators (1/*Ts*) connected as in Fig. 5. The tuned frequency of the integrators is 1/(2 π *T*). A de-tuned integrator can be written as (1+*k*)/(*Ts*) where *k* is a coefficient representing the detuned amount of frequency or time constant.

The simulation was conducted in MatLab with a sampling rate of 100-MHz. Signal amplitude and spectrum was measured while varying the tuning coefficient *k*. The amplitude detection is implemented by a simple first-order low-pass filter (1+*z*^{−1}) followed by a peak detector. Fig. 6 shows the output of the low-pass filter for k = 0% and k = 4%, respectively. At k = 0%, a typical low-level output for a stable SDM loop is shown; at k = 4%, the SDM loop is unstable and its output swings between the quantizer's upper and lower limits in 80 μs.

The low-pass filtered output signal is then peak detected, and Fig. 7 is a plot of the detected peak signal with the third-order continuous-time loop filter tuned from −15% to 15%. The output signal is obviously a two-state 1-bit digital signal. The transition point from an unstable to a stable state is at k = 4%, i.e., 4% away from perfectly tuned frequency. A simple tuning algorithm is to stop at this 4% point, which means a tuning accuracy of 4%. A 4th-order loop filter was also simulated and the tuning response is shown in Fig. 8. The transition is at 2%, indicating a tuning accuracy of 2% that can be reached with the 1-bit tuning scheme.

SECTION IV

## ASYMMETRICAL TUNING

The simulation results in Fig. 7 and 8 show an asymmetrical tuning response. The SDM loop becomes unstable for a positively detuned loop filter, but not for a negatively detuned one. This is because a positively detuned loop filter will increase the noise-shaping gain of the SDM loop; for a SDM that is purposely designed to operate in and/or close to unstable state, such an increase in noise-shaping gain can easily make the loop unstable.

This can be mathematically demonstrated. The noise transfer function (NTF) for the loop filter H(z) as in equation (1) can be written as
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$$NTF = {1\over 1+z^{-1}H(z)}\eqno{\hbox{(3)}}$$If the loop filter H(z) is detuned, the NTF will be
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$$NTF = {1\over 1+z^{-1}(ze^{j2\pi f'})}\eqno{\hbox{(4)}}$$where *f*′ is the amount of detuned frequency. Fig. 9 shows the NTF with 2%, −2%, and 0% detuning for the third-order loop filter simulated in Section III. As can be seen, at 0% detuning, the third-order loop operates normally with a noise-shaping gain of l8 dB. A 2% detuning causes a much distorted noise-shaping curve with an increased noise-shaping gain to 27 dB, forcing the modulator to operate in less linear mode. On the other hand, a −2% detuning reduces the gain slightly, which does not cause any instability. Although it is difficult to theoretically predict the exact transition point of detuning, at which the loop becomes unstable, it can be easily found by simulation. The simulation conducted in the last section shows a transition point of 4% for the third-order 3-bit SDM.

Because of the asymmetrical tuning response, the 1-bit digital tuning must start from the unstable side, i.e., positively detuned side, tuning toward stable side. Also the tuning needs to be held once it reaches the unstable-to-stable transition point. For automatic frequency tuning, this would require the tuning to be kept in the transition region so that the automatic tuning process can be sustainable.

A novel 1-bit digital tuning technique for a continuous-time filter is presented with the use of unstable sigma-delta modulation. The 1-bit digital tuning signal is generated by detecting the stability of a highly unstable sigma-delta modulation loop. Simulations on a 3rd-order and a 4th-order 3-bit continuous-time sigma-delta modulation loops show up to 2% tuning accuracy with the 1-bit tuning technique.