• Abstract

A Low Energy Two-Step Successive Approximation Algorithm for ADC Design

This paper presents a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Calibration registers are used to reduce the error of the most significant bits conversion due to the usage of a smaller capacitor array. Experiments were carried out on a 10-bit SAR-ADC designed using TSMC 0.18 μm CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.

SECTION I

Introduction

The successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications such as wireless sensor nodes, designing low power, and low energy ADC is one of the major challenges. For SAADC, the dominant power dissipation sources are the comparator and the switching in the DAC capacitor array.

Traditional successive-approximation ADC uses a well-known binary tree search method to determine the bit values during the conversion [1], [2], [3]. The conversion starts from the MSB and continues towards the LSB. The first conversion step is to charge up the whole capacitor array to half Vref where Vref is the reference voltage of the maximum detecting input range. Depending on the value of the input, the individual capacitor in the array is charged/discharged in the subsequent conversion cycles. For a 10-bit system, the switching energy of decoding the MSB would be as large as 255 times as of decoding the LSB, due to the larger size of the capacitor at the MSB.

A traditional successive-approximation ADC architecture is shown in Fig. 1. The converter consists of a comparator latch, a successive approximation register (SAR), and a binary weighted capacitors DAC. The output of the DAC (Vy) is charged by connecting the bottom plate of the capacitors to either ground or Vref, and the decoding bit is then determined by checking whether the voltage of the capacitor array (Vy) is greater or smaller than the reference ground (Vx). The process is repeated for the other bits moving towards the LSB, until all the bits are decoded.

Fig. 1. Traditional successive approximation architecture based on a charge redistribution principle.

In [4], Lampinen et al. proposed a double SA algorithm, which has two phases, to reduce the switching energy. The first phase is a nonlinear range selection in which the coarse level of the signal is found in a logarithmic fashion and it is not necessary to go through all the upper bits as in the traditional SA algorithm. The second phase is a linear binary tree search phase similar to the traditional method. In the nonlinear range selection phase, if the input voltage level is low, less number of capacitors is charged up and hence the switching energy is reduced. However, it is still needed to charge up the whole capacitor array with higher voltage, when the input is comparatively high.

In [5], Ginsburg et al. proposed a split capacitor array architecture which splits the largest capacitor of the array into a binary scaled sub-array to maximize the energy savings during switching. By carefully design, the split array avoids throwing away charge that has been stored onto the array by charge recycling during “down” transition. For “down” transition in which the voltage of the capacitor array decreases, switching energy is reduced significantly. So for output codes with smaller values where more “down” transitions occur in the array during the conversion, high switching energy saving can be achieved. However, for other codes that have larger output value, more “up” transitions occur and the energy saving would then be minimal.

In this work, we want to tackle the following problem: “Can we further reduce the switching energy regardless of the input voltage value while at the same time maintaining the requirements of the conversion resolution?”. We propose to use two-capacitor-arrays architecture to reduce the switching energy. A smaller size of capacitor array is used to determine the MSB conversion. For LSB conversion, a full size capacitor array is used and the temporal correlation of the signal is exploited to reduce the switching energy. Correction phase and calibration registers are introduced to eliminate the error at the MSB conversion due to the use of a smaller DAC capacitor array.

SECTION II

Motivation

We use a 6-bit SA-ADC as an example for illustration. For traditional conversion algorithm, the Vref is divided into 64 equal size regions, in which the input is compared with and then digitized into. The conversion can be viewed as composed of two parts: the first is the decoding of the upper 3 bits (MSBs) and the second is the decoding of the lower 3 bits (LSBs). As an example of ZERO Volt, the total switching energy in the first part is 55Co(Vref)2, based on the capacitance of 32Co (MSB, b5), 16Co (b4) and 8Co (b3), and the total capacitance of the capacitor array of 64Co.

One way we can reduce the switching energy of the first part is to use smaller size of capacitors for b5, b4 and b3, as shown in Fig. 2. The total switching energy is (55/8)Co(Vref)2. It can be seen that the energy is reduced by 8 times because a capacitor array of 8 times smaller size is used for the MSB conversion. The energy saving is achieved regardless of the input values. From the above argument, it is shown that we can use a separate and smaller size of weighted capacitors DAC to convert the MSBs, and use a traditional weighted capacitors DAC to do the LSBs conversion. Significant switching energy can then be saved. Fig. 3 shows that switching energy consumption for the traditional and the proposed method.

Fig. 2. Size-reduced weight capacitor DAC for first part.
Fig. 3. (a) Over-estimation error (estimated code = 101, correct code = 100). (b) Under-estimation error (estimated code = 101, correct code = 100).

In this work, we propose a novel two-step search algorithm and a split-capacitor architecture using two binary-weighted capacitor arrays with unequal sizes to reduce the switching power. This method can reduce the switching energy for all range of input voltage level without changing the conversion resolution requirement. It separates the operation into two phases. In the first phase, smaller-sized capacitors are used for the coarse-level-search to determine the values of the most significant bits. In the second phase, typically-sized capacitors are used for fine-level-search to determine the values of the least significant bits where the voltage resolution in each step is finer. The switching energy is reduced dramatically.

SECTION III

Proposed SA Conversion Algorithm

The proposed architecture is shown in Fig. 4. The converter consists of a SAR with control logic, two sets of binary weighted capacitors DAC and two comparator latches (one for coarse-search and one for fine-search), a sample-and-hold circuit, and memory storage.

Fig. 4. Proposed two-step successive approximation ADC with correction.

One of the issues to use a small size capacitor for the coarse-level conversion is the accuracy and resolution issue due to the parasitic capacitance and also the comparator offset. With a n-bit binary weighted capacitor array, we can assume the accuracy and resolution is up to ± 1 LSB which is equal to (1/2n)Vref. For traditional SA-ADC, this resolution and accuracy is acceptable. However, for our 2-phase approach, in the first phase, the small-size capacitance array is used to determine the m-bit MSB. The error can be up to 1/2(nm))Vref and this will seriously affect the accuracy performance of the ADC. Fig. 5 shows an example. In (a), assume the first phase generate a 3-bit MSB code with 101. Ideally, it means Vin is within the range of 0.625Vref and 0.75Vref. However, if due to the accuracy and resolution issue, the actual output voltage Vcoarse of the ADC array is not 0.625Vref for code 101, but is smaller, e.g., 0.57Vref (within ± 1 LSB error of the coarse-level conversion), then when the Vin is equal to 0.59Vref phase-1 will still generate a 101 code. In phase-2, even when a larger-size DAC is used for a better resolution, the best decoding result is 101000. The correct decoding value should be 100101 and the error introduced is large. Similar error will occur when the actual output voltage Vcoarse of the DAC array is higher than that represented by the first phase decoded output, as shown in Fig. 5(b), noted as an underestimation error.

Fig. 5. Energy curve for Traditional Method and Proposed Method.

To solve this accuracy and resolution issue, we add a correction phase between the phase-1 coarse-level conversion and phase-2 fine-level conversion. In the first three clock cycles, the MSBs (b5, b4, b3) are estimated by the coarse-level DAC array. In the 4th and 5th cycle, we test whether the estimated MSB has under-estimation or over-estimation error. We load the estimated MSBs to the large-size fine-search DAC array and assign zeros at the LSBs (b2, b1, b0). The voltage of the DAC array (Vfine) is compared with Vin. If Vin is smaller than Vfine, this indicates that there is an over-estimation issue, then we subtract the estimated MSB by 1 and reload into the fine-search DAC array in the next clock cycle. Otherwise, in the 5th clock cycle, we test whether there is under-estimation by assigning ones at the LSBs (b2, b1, b0) in the fine-search DAC array. The voltage of the DAC array (Vfine) is again compared with Vin. If Vin is larger than Vfine, it indicates there is an under-estimation issue, then we increase the estimated MSB in the fine-search DAC array. After that we go into the fine-search second phase to obtain the LSBs conversion. The MSBs are already available in this phase, and the fine-search conversion is carried out in a similar fashion as the traditional method.

From the above discussion, we add an intermediate phase, which consists of 2 cycles to determine whether there is under-estimate or over-estimate error and correct back the MSBs if there are errors. Note that in each conversion, the MSBs of the fine-search DAC are loaded from the estimated values obtained from the coarse-level conversion. Different from the traditional conversion, they are not reset to zero at the end of the conversion. Instead, the previous values are kept. This is crucial for the energy saving as for most of the data conversion, the data is temporally correlated and the value of the data between two sampling periods are usually close to each other. Thus the MSBs of two consecutive data are close to each other and when we reload the MSBs at the fine-search capacitor array, most of the time the charge/discharge status of the capacitors are not changed and hence the switching of these large capacitors are much reduced.

The two additional cycles for the intermediate phase pose some energy overhead as additional comparison is required. To reduce the energy overhead we want to reduce the average number of additional comparison. When a particular digital code (xyz) has the coarse-above-fine characteristics, i.e., Vy,coarse (xyz) > Vy,fine (xyz000) over-estimation error will not occur because if Vin is larger than Vy,coarse (xyz), it will always larger than Vy,fine (xyz). Similar situation applied for under-estimation error checking. Thus if we know the characteristic of the voltage relationship between the fine and coarse-level of DAC output for each code, sometimes we can omit the over-estimation and under-estimation checking and this can save the overhead of the additional comparison. For each MSBs' digital code, we use a 2-bit memory to store the above voltage characteristic. The register value represents three different situations for the code, UN-ASSIGNED, COARSE-BELOW-FINE [Fig. 5(a)] and COARSE-ABOVE-FINE [Fig. 5(b)]. The values of the register are updated during the conversion process and they only need to be updated once. Depending on the value of the memory for the particular code and adjacent codes, the error-checking process in the intermediate phase can be bypassed and the number of additional comparison is reduced.

When the over-estimation or under-estimation error is detected, the MSBs in DAC array (Vfine) is required to be subtracted or added one. If the MSB is 100 and required to be subtracted by one, all three MSBs have to be toggled. It would consume a large amount of switching energy, due to the large capacitance in MSBs. To reduce the energy overhead for addition and subtraction, the MSBs capacitors are split into the pattern that would only require one capacitor charged/discharged for the operation of the addition or subtraction, regardless of the code values. Fig. 6(a), (b) shows the original MSBs capacitor and the split-version. In (b), the ADD is the active HIGH signal of addition; the SUB is the active LOW signal of subtraction and the SP1 is to control number of capacitor required to be connected to Vref. For example, if the MSB is 110, in (a), the b5 and b4 are connected to Vref, and the total capacitance would be 48Co(32Co+16Co). In (b), the b5, b4, SP1 and SUB are connected to Vref, the total capacitance would be also 48Co(24Co+ 8Co + 8Co + 8Co). However, the addition operation is performed by changing the ADD signal from zero to Vref. And the subtraction operation is performed by changing the SUB signal from Vref to Gnd. The switching energy for addition and subtraction is fixed, regardless of code values.

Fig. 6. (a) Original MSBs, (b) the split version of MSB in fine-search capacitor array, for addition and subtraction.
SECTION IV

Switching Energy Analysis

From Fig. 1, Vin is first sampled into the DAC capacitor array. The energy required to charge the whole capacitor array with the voltage of Vin is TeX Source $$E_0 = {1 \over 2}C_{\rm total}V^2_{\rm in}=\left({1 \over 2}\right)2^nC_oV^2_{\rm in}\eqno{\hbox{(1)}}$$E1 for checking the MSB is equal to [5] TeX Source $$E_1 = -C_nV_{\rm ref}V_{\Delta (n)[1 < -0]} = \left({1}\over {4}\right)2^nC_oV^2_{\rm ref}\eqno{\hbox{(2)}}$$where VΔ (n)[1 < −0] is the voltage difference across the capacitor Cn between time-1 and time-0. At time-2, the (n−1)th bit is decoded. Either “up” transition or “down” transition occurs. E2down is given by [5]: TeX Source \eqalignno{E_{2({\rm down})} & = -C_{n-1}V_{\rm ref} V_{\Delta(n-1)[2 < -1]} = \left({5 \over 16}\right)2^nC_oV^2_{\rm ref}\quad {\hbox{(3)}}\cr E_{2({\rm up})} & = \left({1 \over 16}\right)2^nC_oV^2_{\rm ref}\quad {\hbox{(4)}}}

The energy consumption for decoding the rest of the bits can be analyzed using the same method. In [5] charge recycling and split capacitor techniques are used to reduce the down conversion energy and E2up and E2down are given by: TeX Source $$E_{2({\rm up})} = E_{2({\rm down})} = \left({1 \over 16}\right)2^nC_oV^2_{\rm ref}\eqno{\hbox{(5)}}$$

B. Proposed Two-Step SR-ADC

From Fig. 4, Vin is sampled into Cs initially. The energy required to charge up Cs to Vin is TeX Source $$E_0 = {1 \over 2}C_sV^2_{\rm in}\eqno{\hbox{(6)}}$$The calculation of the switching energy is similar to the traditional approach, except that the sizes of the capacitors are different. Simply, the E1 of charging up the bottom plate of Cn to Vref, can be expressed as [5] TeX Source $$E_1 = -C_nV_{\rm ref}V_{\Delta(n)[1 < -0]} = 2^{(n-m-2)}C_oV^2_{\rm ref}\eqno{\hbox{(7)}}$$For “Up transition” and “Down transition”, the E2up and E2down are expresses as: TeX Source \eqalignno{E_{2({\rm down})} & = -C_{n-1}V_{\rm ref}V_{\Delta(n-1)[2 < -1]} = 2^{(n-m-4)}5C_oV^2_{\rm ref}\quad \hbox{(8)}\cr E_{2({\rm up})} & = 2^{(n-m-4)}C_oV^2_{\rm ref}\quad \hbox{(9)}}

We can see that the energy consumption due to the “up” and “down” transition is much lower than the traditional approach, due to the reduction of the capacitance.

In the detection phase-1 and phase-2, when the over-estimation error or under-estimation error is detected. The MSBs are required to be subtracted or added by one, and the switching energy of subtraction Esub and of addition Eadd are given by: TeX Source \eqalignno{E_{\rm sub} & =\left({1 \over 2}\right)2^{(n-m)}C_oV^2_{\rm ref}\quad \hbox{(10)}\cr E_{\rm add} & =\left({1 \over 2}\right)\left(2^{(n-m-1)}-1\right)C_oV^2_{\rm ref}\quad \hbox{(11)}}

In the detection phase-2, the LSBs are required to set the ONEs for checking the under-estimation. Since the bit-(n-m) will be eventually set to ONE for decoding, the switching energy Eones for setting LSBs to ONEs is given by: TeX Source $$E_{\rm ones} = \left({1 \over 2}\right)\left(2^{(n-m-1)}-1\right)C_oV^2_{\rm ref}\eqno \hbox{(12)}$$

We compared the switching energy consumption of the traditional, charge recycling [5] and proposed approaches using MATLAB for a 10-bit capacitor array. The input data is swept from 0 to 1023 consecutively. The results are shown in Fig. 7. We can see that using the charge recycling approach [5], the energy saving is diminishing when the output code is large. For the proposed two-step approach, since the switching capacitance is dramatically reduced, the energy saving is much significant. At the smallest and largest output codes, the switching energy saving over the traditional SA-ADC and the charge-recycle SA-ADC are 93.3% and 87.7%, and 83.4% and 87.7%, respectively. The average switching energy saving over all the output code, when comparing with the traditional SA-DAC and the charge-recycle SA-ADC, are 92.4% and 87.9%, respectively. We also used real example data to simulate the actual energy saving. Instead of using continuously swept input data, we collected the sampled data at 44 kHz from a musical file and used the data as the input to the ADC. Fig. 7 summarizes the switching energy for the three different ADC architecture. From Fig. 7, we can see that the proposed 2-step approach consume much less energy than the other two approaches.

Fig. 7. (a) Switching energy versus input code for a 10-bit capacitor array, (b) Switching energy versus music file.
SECTION V

Simulation Results

A 10-bit capacitor array using the proposed two-step search approach was designed using TSMC 0.18 μm CMOS technology with metal-insulator-metal capacitor. We divided the bits into two equal groups of 5, i.e., the number of bits in the coarse-search phase (MSBs, b9-b5) and the fine search phase (LSBs, b4-b0) regions are all equal to 5 (m = 5). We also implemented a design using traditional approach. The simple sequencer and code register designs are used, with the custom made Flip-flop, which built on the C2MOS register. The simple P-type comparator latches with power gating switch are used. The proposed and traditional designs were implemented into a single chip to share with the same capacitor array and comparators, as shown in Fig. 8. The proposed two-step approach is occupied 11% more layout area than the traditional, due to the capacitors in coarse-search, memory storage with logic and one comparator.

Fig. 8. SA-ADC chip layout (traditional and proposed approaches implemented using the same capacitor array).

For the proposed approach, since the detecting resolution required is 5-bit and 10-bit: (1/32)Vdd and (1/1024)Vdd in the coarse-search and fine-search respectively. The required biasing current for the comparator latch used in coarse-search, is smaller than the one used in fine-search. We use simple control logic for testing the over-estimation and under-estimation errors, and use the simple register bank for storing 32 digital codes characteristic.

HSPICE simulation were done to verify the function and compare the energy consumption of the two architecture. The designed parameters are as follows: n = 10 bit, Vdd = 1 V, Vref = 0.65, the unit capacitor Co = 23.2 fF, sampling frequency (fs) = 128 kHz. A data swept from 0 to 1023 was used as the input to the ADC for energy consumption comparison. The simulation results of the energy consumption for different inputs of the traditional and proposed approaches are shown in Fig. 9. The energy components of the comparator, digital controller and the capacitor array are shown. The comparator power of the traditional approach is larger than of the proposed approaches, due to the comparator in the coarse-search would consume less power. The controller power of the proposed approach is larger than of the traditional, due to the additional logic control for detecting phase, and additional memory access in the proposed approach. The capacitor switching power is much more in the traditional approach, due to the large capacitance in the MSBs. From Fig. 8, the average energy saving over all the output code is 51.8% when compared with the traditional SA-ADC.

Fig. 9. HSPICE simulation of traditional and proposed approaches.
SECTION VI

Conclusion

A low energy two-step successive approximation algorithm for ADC is proposed utilizing a two-capacitor-arrays architecture to reduce the switching energy. An ADC with a resolution of 10-bit was designed, and its operations was verified by HSPICE simulation.

Footnotes

R. Y.-K. Choi, C.-Y. Tsui are with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China eericky@ust.hk, eetsui@ust.hk.

References

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M. D. Scott, B. E. Boser, K. S. J. Pister

Solid-State Circuits Conference, 2002-09, 255–258

2. A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS

D. Draxelmayr

IEEE ISSCC 2004, vol. 1, p. 264–527, 2004-02

3. A 1 V supply successive approximation ADC with rail-to-rail input voltage range

T. Yoshida, M. Akagi, M. Sasaki, A. Iwata

ISCAS, vol. 1, p. 192–195, 2005

4. Novel successive-approximation alogrithms

H. Lampinen, P. Perala, O. Vainio

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Keywords

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capacitors, analogue-digital conversion, capacitor switching

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This paper appears in:
International Symposium on Circuits and Systems
Issue Date:
2009
On page(s):
17 - 20
ISBN:
N/A
Print ISBN:
978-1-4244-3827-3
INSPEC Accession Number:
10760256
Digital Object Identifier:
10.1109/ISCAS.2009.5117674
Date of Current Version:
26 Jun, 2009