As system on chip (SOC) integrates more and more functions, percentages of standard digital blocks also increases. Though the world is analog, digital circuit can provide high performance and cost efficient signal processing. In high performance SOC design, the data converter becomes the bottle neck and the most challenging mixed-signal block. Several applications such as wireless infrastructure, optical networking, high accuracy data acquisition systems, measurement and medical instruments, need analog to digital converters (ADC) with resolution above 16 bits. While in wireless LAN, UWB and inter-connectivity applications, ADCs with hundreds Mega Hertz sampling rate are needed. It is a big challenge to design and test ADCs with such high performances.

In traditional testing and measurement procedures, the linearity of signal must be three or four bits higher than that of under test ADC. This will boost the testing cost when the resolution of ADC becomes higher than 16 bits. The fast rising cost of testing high performance mixed signal circuits leads to the seeking of other testing strategies. Several algorithms that allow low linear stimuli to be used in test of high linearity ADC were presented in [1], [2], [3]. Experimental results of first two papers showed that 16 bits ADC can be tested within reasonable accuracy using stimulus with only 7 bits linearity. In [3], 12 bits ADC can be well tested by using 8 bits DDEM DAC. Though these algorithms were presented for standalone production test, all of them can be used in built-in self-test (BIST) applications.

Rising cost of testing and complexity of SOC also drive the development of the BIST technique. Advantages of implementing BIST are lower cost of test, better fault coverage, shorter test time, etc. As for ADC BIST, DSP, memory, and stimulus generator are needed to be built on chip. In SOC application, DSP and memory in digital blocks can be easily shared by ADC BIST. Most reported ADC BIST strategies require on chip high linear stimulus generator [4], [5], [6], which is the most challenging block in ADC BIST. If low linear and accurate stimulus generator can be used in ADC BIST, the area, power consumption, and design difficulty will become more optimistic. This also allows BIST based self-calibration to be used in the design of ADC that is deeply integrated in a SOC.

In this paper, cost effective signal generators are presented. Generated signals have low linearity but meet the requirements of algorithms that can identify ADC's nonlinearity by using low linear input signal. In Section II, the stimulus error identification and removal (SEIR) method is briefly reviewed first. Then, feasible stimulus patterns are investigated. In Section III, two types of signal generators are presented. Simulation results are given in Section IV.

SECTION II

## COST EFFECTIVE ADC BIST METHOD

### A. Stimulus Error Identification and Removal

Fig. 1(a) shows the quasi-static linearity test procedure with ideal input ramp signals. *V*_{o} is the ADC's output code values, *S*_{i} is number of samples when *V*_{o} equals to *i*. *T*_{i} represents the *i*th transition voltage level of ADC and *I*_{i} is the *i*th transition voltage level of ideal ADC. Since offset and gain error can be easily removed, we can assume *I*_{0} = *T*_{0} and *I*_{N − 2} = *T*_{N − 2}. Thus, we have
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$$I_{i}= T_0{{T_{N-2} - T_0} \over {N-2}}\cdot i\quad i = 0, 1\ldots N-2\eqno{\hbox{(0)}}$$The *INL* corresponding to output code *i* is the difference between *T*_{i} and *I*_{i}. *INL*_{i} can be calculated if transition level *T*_{i} is known.
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$${\rm INL}_{i} = {T_i - I_i \over T_{N-2}-T_0}(N-2)\eqno{\hbox{(1)}}$$Time *t* is normalized to [0, 1], so the ideal input ramp signal can be expressed as
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$$V(t) = T_0 + (T_{N-2} - T_0)\cdot t\eqno{\hbox{(2)}}$$And transition level can be expressed in terms of transition time *t*_{i}
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$$T_i = T_0 + (T_{N-2} - T_0)\cdot t_i\eqno{\hbox{(3)}}$$where *t*_{i} can be easily acquired from output code samples.

In real test environment, input ramp signal is nonlinear and can be expressed as the sum of an ideal ramp and the nonlinear part.
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$$V(t) = T_0 + (T_{N-2} - T_0)\cdot t + \sum^{M}_{j=1}F_j(t) +\varepsilon\eqno{\hbox{(4)}}$$where *F*_{j}(*t*) is a set of basis functions and ∊ is the residual part of approximation which can be very small if *M* has reasonable value.

Fig. 1(b) shows the quasi-static linearity test procedure with two non-linear input ramp signals. The only difference between these two signals is a constant offset Δ, *V*_{2}(*t*) = *V*_{1}(*t*) − Δ. Similar with (3) we can get
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$$\eqalignno{T_i & = T_0 + (T_{N-2} - T_0)\cdot t^{(1)}_i + \sum^{M}_{j=1}a_j F_j\left(t^{(1)}_i\right) + \varepsilon& {\hbox{(5)}}\cr T_i & = T_0 + (T_{N-2} - T_0)\cdot t^{(2)}_i + \sum^{M}_{j=1} a_j F_j\left(t^{(2)}_i\right) + \varepsilon -\Delta& {\hbox{(6)}}}$$These two equations contain non-linearity information of ADC and input ramp signal. From (5) and (6) we can get an equation contains only non-linearity information of input ramp signal.
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$$\eqalignno{& (T_{N-2} - T_0)\cdot \left(t^{(2)}_i - t^{(1)}_i\right) \cr& \quad = a_j \left(\sum^M_{j=1}F_j\left(t^{(1)}_i\right)-\sum^M_{j=1} F_j\left(t^{(2)}_i\right)\right)+\Delta\cr& & i = 1, 2\ldots N-3\quad \hbox{(7)}}$$Now the number of equations is *N*−3−Δ and the number of unknown parameters is *M* + 1. By using the least square method to solve these equations, we can get coefficients that represent the nonlinear part of input ramp signal. The real transition level *T*_{i} of ADC can be calculated from (5) or (6).

### B. Signal Patterns

The algorithm requires two input signals to be identical and the offset between them to be constant, which is difficult to be achieved on chip.

Consider input signals with different nonlinear characteristics. We can still use the same type of basis function but with different coefficients to approximate their nonlinear parts. From (4) and (5), we get
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$$\eqalignno{& (T_{N-2} - T_0)\cdot \left(t^{(2)}_i - t^{(1)}_i\right) \cr& \quad =\sum^{M_1}_{j=1}a_jF_j\left(t^{(1)}_i\right)-\sum^{M_2}_{j=1} b_jF_j\left(t^{(2)}_i\right)+\Delta \cr& & i = 1, 2\ldots N-3\quad {\hbox{(8)}}}$$Now the number of equations is *N*−3−Δ and the number of unknown parameters is *M*_{1}+ *M*_{2}+ 1. Coefficients can be calculated from these equations by using the least square method. But neither of these two sets of coefficients can represent its nonlinearity.

Another relationship of two signals that can be easily realized is gain.
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$$V_2(t) = \beta\cdot V_1(t)\eqno{\hbox{(9)}}$$The value of β should be close to 1 so that *V*_{2}(*t*) can stimulate nonlinearity near the full scale range. Repeating formula derivations in the previous section, we get
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$$\eqalignno{& T_0 + (T_{N-2} - T_0)\cdot t^{(1)}_i \cr& \quad =\beta \cdot \left[T_0+(T_{N-2} - T_0)\cdot t^{(2)}_i\right]\cr& \qquad + a_j \sum^M_{j=1}\left[\beta \cdot F_j\left(t^{(2)}_i\right) - F_j\left(t^{(1)}_i\right)\right]\cr& & i = 1, 2\ldots N-3\quad {\hbox{(10)}}}$$In this set of equations, the number of equations is much bigger than that of unknown parameters. But these equations are nonlinear with β and *a*_{j}, which cannot be expressed as a matrix. In order to get the solution, let β be equal to a tentative value β′ which is determined when the circuit was designed. After a number of iterations, the solution will have the minimum difference between β and β′ [7].

SECTION III

## STIMULUS GENERATORS

BIST schemes for internal ADC blocks in SOC must have very small cost overhead and stimulus generators should not consume much power or area. The most simple and direct implementation is a charge pump as shown in Fig. 2(a). In order to generate a very slowly rising ramp signal, the load capacitor should be very large even when the charging current is very small. Large capacitors implemented on chip will occupy large die area.

The alternative way is to generate a triangle voltage signal as shown in Fig. 2(b). In this circuit, charge and discharge currents change with output voltage. Output resistance of transistor changes with output voltage even both P1 and N1 are operating in saturation region [8]. Usually, drain currents of P1 and N1 are assumed to be the same, so the charge time and discharge time are the same. But in real situation, charge current and discharge current are different due to the mismatch between P1 and N1.

The differential structure showed in Fig. 2(c) can remove charge and discharge current mismatch and provide large output range. In the charging phase, output voltages can be expressed as
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$$\eqalignno{V_{op}(t) & = {I_1 \over C}t + V_{op}(0)\quad{\hbox{(11)}}\cr V_{om}(t) & = {-I_2 \over C}t + V_{om}(0)\quad {\hbox{(12)}}}$$The differential output voltage is
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$$V_{o}(t) = V_{op}(t) - V_{om}(t) = {I_1 + I_2 \over C}t + V_{op}(0) - V_{om}(0)\eqno{\hbox{(13)}}$$In the discharging phase, output voltage is
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$$V_o(t) = - {I_1 + I_2 \over C}t + V^\prime _{op}(0) - V^\prime _{om}(0)\eqno{\hbox{(14)}}$$The differential output voltage has identical rising and falling slope no matter what the current value is.

### A. Exponential Signal

In most situations, ramp signal, triangle, and sine wave signal were used in histogram based quasi static linearity test of ADC. However, many voltage signals can be used in the histogram method, as long as these signals can be clearly expressed in terms of time. Exponential voltage signal will be a good choice since it can be easily generated from charging a resistor and a capacitor.

Fig. 3(a) shows a circuit that can generate two exponential voltage signals. This generator consists of a simple charge pump and a unit gain buffer. In switch capacitor application, a buffer is necessary for driving sampling capacitor. Another buffer is needed to separate tow low impedance nodes. Cascade transistors can be added to increase output resistors. The output resistors can also be increased by adding gain boost transistors to the gates of P1 and N1, which will not decrease output voltage range.

From Fig. 3(a), we can get
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$$\eqalignno{V_1(t) & = I \cdot R + (V(0) - I \cdot R)\cdot e^{-{t \over RC}}\quad {\hbox{(15)}}\cr V_2(t) & = {R_2 \over R_1 + R_2}V_1(t)\quad {\hbox{(16)}}}$$where *R* = *r*_{o}//(*R*_{1}+ *R*_{2}), *r*_{o} is the output resistance of MOS transistor. *I*, *r*_{o}, and *R* will change with output voltage, which will cause nonlinearity to *V*_{1}(*t*). After fabrication, the real output voltages can be expressed as
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$$\eqalignno{V^\prime_1 (t) & = I \cdot R + (V(0) - I \cdot R)\cdot e^{-{t \over RC}} +\sum^M_{j=1}a_jF_j(t)+\varepsilon\quad {\hbox{(17)}}\cr V^\prime_2(t) & =\beta^\prime \cdot V^\prime_1(t)\quad {\hbox{(18)}}}$$where β′ is fixed after fabrication, but has a small difference from the nominal value β = *R*_{2}/(*R*_{1}+ *R*_{2}) due to nonideal processes.

Fig. 3(b) shows the output voltage waveforms of the exponential generator. When these two signals are used in SEIR, we can get a set of equations
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$$\displaylines{(1-\beta)\cdot IR + (V(0)-IR)\cdot (e^{-{t^{(1)}_i \over RC}}-\beta e^{-{t^{(2)}_i \over RC}})\hfill \cr\hfill \quad = a_j \sum^M_{j=1}\left[\beta\cdot F_j\left(t^{(2)}_i\right) - F_j\left(t^{(1)}_i\right)\right]\quad i = 1, 2\ldots N-3\quad {\hbox{(19)}}}$$This set of equations can be solved by using the same method as (10). Potential problems of using two exponential signals with a small gain between them are the number of iterations and convergence difficulty. The difference between β′ and β caused by nonideal processes can be very small with good layout matching. So the converge speed can be very fast.

The nonlinearity of OTA and resistors in the buffer cause additional nonlinearity to the output voltage. Through good layout matching, ratio of resistors can be matched very well so that the nonlinearity of resistors can be neglected. The inverting buffer provides better linearity than noninverting buffer since it keeps input voltage of OTA very small. The output voltages of buffer are
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$$\eqalignno{V_{o1} & = -{A \over A + 2}V_1(t)\quad {\hbox{(20)}}\cr V_{o2} & = - {A \over A + 2}\cdot {R_2 \over R_1+ R_2}V_1(t) = \beta \cdot V_{o1}\quad {\hbox{(21)}}}$$where *A* is the open loop gain of OTA and changes with output voltage. Equation (21) has the same pattern with (9), and the nonlinearity can also be approximated by basis functions.

### B. Triangle Signal

Fig. 4(a) shows another low cost generator that can generate two triangle signals with a small offset between them. An OTA is used as inverting unit gain buffer to accommodate switch capacitor application and meanwhile generate the small offset. The output voltage of the charge pump is
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$$V_x(t)= V_x (0) + {I \over C}\cdot t\eqno{\hbox{(22)}}$$For the same reason as part *A*, nonlinearity of resistor is neglected and only OTA's nonlinearity is considered. The output voltage of buffer can be expressed as
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$$\eqalignno{V_{o1} & = -{A \over A + 2}\cdot V_x(t)&\hbox{(23)}\cr V_{o2} & = V_{o1} + 2V_{\rm offset}- {4 \over A + 2}V_{\rm offset}&\hbox{(24)}}$$The third term in the right side of (24) is the extra offset caused by finite gain of OTA. Since *A* is nonlinear, this term cause extra nonlinearity to *V*_{o2}, which will affect the accuracy of SEIR. The offset voltage is about 0.5% of full scale range. Assuming open loop gain of OTA is larger than 66 dB, the magnitude of this term is about 10^{− 5}, which is small enough in 16 bits ADC test.

Due to noise and environmental change, charge current and offset voltage cannot be constant during test procedures. Inconstant charge current and offset voltage decreases the accuracy of SEIR. One way to relieve this influence is interleaving *V*_{1}(*t*) and *V*_{2}(*t*) [3]. Fig. 4(b) shows the interleaved output voltages. The opamp has 80 dB DC gain and 45 MHz unity gain frequency.

Both exponential signal generator and triangle signal generator has low cost of power and area. The charge pump can be very simple without enhancement of output resistor and current linearity. Open loop gain of the OTA does not need to be large or have good linearity when output voltage swing in the range of ADC's full scale.

SECTION IV

## SIMULATION RESULTS

Two stimulus generators presented in the previous section were built in TSMC 0.18 μm process. To verify whether a simple charge pump is good enough to generate signals used in the SEIR method, output of the triangle generator was exported into Matlab simulation. A period of ramp was selected in the output triangle wave for simulation. Linearity of this ramp is 1.3% which is slightly better than 6 bits. The constant offset voltage which is 1% of full scale range is added before buffer. An additive noise with 1 LSB was added to the ramp during simulation. Behavioral model of a 16 bits ADC with 10 LSBs INL was built. 30 sinusoidal basis functions were used to approximate the nonlinearity. Both true and estimated INL of ADC were plotted in Fig. 5(a) and (b), the blue curve is estimated INL, and it tracks real INL with very small error. Estimation errors of all transition levels' *INL*_{i} were plotted in Fig. 5(c), and the biggest error is 0.65 LSB. The estimation error of ADC's INL is 0.22 LSB. Other cases that real INL changes from 10 to 0.4 are simulated, estimated INL errors are below 0.7 LSB, which means real INL does not affect estimation algorithm.

Low cost stimulus generators are necessary for ADC BIST in SOC. Adapting SEIR method that was reported for standalone production test for ADC BIST decreases requirements of the linearity of stimulus. Signal patterns that can be used in low cost BIST scheme are investigated. Low cost charge pump can be used in stimulus generators. A differential charge pump structure is proposed for identical charge and discharge rate and large output voltage range. Two cost effective stimulus generators are proposed. Simulation result shows that output voltage of charge pump can be used to test 16 bits ADC.