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  • Abstract

Hybrid BiST Solution for Analog to Digital Converters With Low-Cost Automatic Test Equipment Compatibility

The cost of testing mixed signal circuitry with conventional analog-stimulus is significantly higher than digital circuitry due to higher cost Automatic Test Equipment (ATE) required for generation of analog stimulus. Multiple variants of low cost testers have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hardware cost. Systems containing mixed-signal/RF components can thus not be tested on such ATE due to the cost and limitations of analog/RF stimulus and measurement modules. This paper proposes a hybrid BIST scheme for Analog to Digital Converters (ADCs) to enable full production-quality testing with low cost ATE. The two major challenges addressed are generating the input stimulus, and a fully functional at-speed test to maintain the test quality of a pure analog ATE solution.



The primary gating factor for using low cost ATE in mixed signal test is generation of the input test stimulus on the Device under Test (DUT), as low cost ATE cannot provide it externally. External analog stimulus generation requires complex analog/RF compatible ATE with the associated high cost. Built-in ramp and triangle wave generator circuits have been a subject of research for the last few decades and a large number of solutions have been proposed [1], [2], [3], [4], [5], [6], [7]. Our stimulus generation scheme, discussed later in the paper, is directed at optimizing silicon overhead as well as considering the voltage and clocking limitations of low cost ATE. The ramp generation scheme proposed in [7] is robust for process variation but requires a negative voltage supply available on the DUT which is very rare for modern System on a Chip (SoC) and System in a Package (SiP) systems. We use a single positive supply for all components with a total of two differential clocks; a 50% duty cycle PLL-generated clock may be produced on most low-cost ATE at the required high frequencies. Using phase-shifted limited duty cycle clocks may require greater system resources and may not be within the capabilities of a typical low cost ATE. We also propose the use of a real-time code analysis method instead of the traditional histogram method to reduce the sample gathering interval. The histogram method also requires a large number of data samples to be collected and stored before the analysis can be performed while the realtime code analysis method enables real time calculations for INL/DNL and other essential parameters while additional data is still being collected. We also include an interval-counter which can be shifted out of a scannable register and is used for the characterization calculations. This counter indicates the estimated instantaneous input stimulus value which is essential to perform accurate INL/DNL calculations on ATE with limited computing resources. We use a hybrid scheme as against a fully-scanable scheme as explained in [7] to enable at-speed testing of output pads and paths. This enables at-speed functional testing which may not be feasible for a full-scan scheme while adding topology limitations. A full-scan scheme requires all the data and the overhead bits to be shifted serially, increasing the frequency requirements of the ATE. We do not consider a DSP based approach as proposed in some of the earlier work [7], as an on-chip DSP is less likely to be available for most of the modern DUTs. Analog blocks are increasingly common on digital Application Specific Integrated Circuits (ASICs) and SiPs where access to DSP cores may not be available.



A. Fundamentals

Availability of an on-chip stimulus generator is a crucial factor to eliminate the need of expensive analog testers. A ramp input with a well characterized linear slope can be used effectively for production testing of an ADC with either histogram method or the real-time code analysis method that we have proposed. A lot of interesting work has been done in this area with circuit proposals for ramp generators [1], [3], [7]. Each scheme has its own trade-offs, the main factor being silicon overhead and the stabilization time. We also introduce input clocking requirements as an important constraint. A feedback mechanism is required between the ramp output and the generator circuit to maintain a constant ramp slope. Fundamentally, a ramp generator involves a constant current source which charges a capacitor in a way that the voltage across the capacitor increases linearly.

B. Effect of Process Variation

The basic ramp generator involves an ideal constant current source feeding an ideal capacitor serially. For the ADC to have a constant-slope-constant-period ramp as an input, an exact icharge and capacitance value is essential. If 0 V to VDD is the input swing spec for the ADC, the input ramp should reach VDD at an extract time period t′ for each cycle. Process variations would affect the ramp slope and linearity, and hence make the stimulus of very limited use for production test.

Constant current charging of a capacitor C linearly increases the voltage across the plates, and any process variation causing a change in capacitance would inversely affect the ramp voltage slope. Similarly, any variation in the current drive of the charging circuit would affect the charging time. Formula TeX Source $$C = Q/V, \quad V_{\rm cap} \propto {1 \over C}\ {\rm hence}, \delta V_{\rm Cap} \propto 1/\delta C$$

SPICE simulations run for cold-nominal-hot process corners clearly indicate that for the ramp generator without feedback, a very precise process target would be required to maintain required ramp slope, making it impractical for a commercial production test. A feedback scheme is required for controllability of the ramp; this is essentially a variable feedback which can maintain a constant voltage ramp slope for any process variation in the capacitor or the constant current source. The feedback is required to be dynamic to ensure complete process corner independence.

C. Low-Cost ATE Concerns

Multiple schemes have been proposed for feedback [5], [7] which use some type of feedback path to control bias current depending on mid-cycle samples from the ramp voltage. Limited duty cycle latches are used in [5] to control charging and discharging of a capacitor. The feedback scheme used in our proposal is represented in Fig. 2. The primary concerns for this design to maintain low-cost ATE compatibility were as follows.

Figure 1
Fig. 1. Constant Current Source for Capacitor Charging.
Figure 2
Fig. 2. Feedback Mechanism for Ramp Generator Circuit.
  • Use of minimal possible number of clocks as using multiple clocks may limit multi-site production testing. Also, a low cost tester will have a limited number of clocking resources available.

  • Use of clocks with 50% duty cycle; high speed asynchronous clocks available on low cost ATE tend to be free-running PLL outputs.

  • No additional (or negative) supplies required apart from the native supplies for the ADC/buffers.

D. Feedback Mechanism for Process Independence

A clocked comparator is used to compare the ramp output with Formula at Formula where is the ramp period. Transistor M1 in Fig. 2 is used to reset capacitor C1. C1 is used as per-cycle-charge-storage for the comparator output. Charging conditions for the capacitor C1 are defined as Formula TeX Source $${\rm If}\ V_{\rm ramp} < {{\rm VDD} \over 2}\ {\rm at}\ {T_{\rm per}\over 2},\quad V_{C1} = VDD\ {\rm else}\ V_{C1} = 0\ {\rm V}$$Latches L2 and L3 are toggled by an offset clock to limit the conductive phase of the combination latch. Formula TeX Source $$\Phi 3 = \Phi 1 \cap \Phi 2$$This offset phase Φ 2 is generated out of an oversized gate delay and no additional clocking source is required. When L2 and L3 conduct, capacitors C1 and C2 in Fig. 2 are connected in parallel and a charge sharing current flows to equalize the voltage across each capacitor. Formula TeX Source $$I_{\rm charge{-}sharing} = {d \over dt}\left[{v1 - v2 \over c1 + c2}\right]$$

Voltage across capacitor C2 is used to change the bias current in the constant current source. If the Vramp < Vref at Formula, C1 will charge C2 to a higher voltage value while for Vramp > Vref at Formula, C1 being at 0V, will partially dischare C2, lowering the effective voltage across C2. A reduction in the voltage across C2 would then mean a lower gate bias for the current mirror, reducing load charging current. Capacitor values are designed for 1 pF to minimize the layout area overhead. Settling time for the ramp generator is crucial as the output ramp should be stable in the minimal possible time, since testing of the ADC cannot begin until a consistent ramp slope is obtained. Using wide transistors for latches L2 and L3 would enable rapid charge sharing between C1 and C2 due to increased conductivity. It would also result in Vramp overshoot and undershoot as excessive correction bias may be applied to the constant current source. Transistor widths for L2 and L3 are thus optimized to stablize Vramp in approximately 6–7 cycles. Table I indicates the Vramp-peak overshoot/undershoot values for various width values across process corners.

Table 1
TABLE I Optimizing Feedback Path W/L Ratio for Settling Time vs Output Peak Noise

Our ramp generator feedback design is optimized to ensure the following factors: i) Minimal area overhead—use of 1 pF capacitors, ii) No additional clock requirements—clocks used in the current source are shared, iii) Absence of a negative power supply, iv) Optimized settling time—we tweak the nominal transistor widths to adjust the ramp Vmax settling time to 10 cycles. The effect of process variations on this settling time can be observed in SPICE simulations. The overall ramp generator circuitry with the feedback scheme is represented in Figs. 1 and 2. A current mirror circuit is implemented using semi-telescopic topology and a capacitive load C1 is charged linearly using this current source. The feedback circuit adjusts the gate bias for transistor M1 per cycle to ensure that Vout reaches Formula value at time Formula. The feedback scheme ensures a dynamic process-corner independent stable operation providing positive or negative feedback, depending on the results from the previous cycle.



A digital counter, using in-phase clock resources as the ramp generator discussed above, is used as an interval counter in the BiST scheme. The interval counter acts as an accurate approximation of the ramp stimulus as the ramp generator and the interval counter share clocking resources. The interval counter is added to the BiST sceheme to provide a timing reference and the code-width is optimized to provide adequate number of timing references without excessive silicon or timing overhead. This scheme uses a 4-bit counter with a scannable output, effectively providing one timing anchor for 8-bits of ADC output codes. Increasing the counter width would provide additional timing anchors, effectively resulting in more accurate DNL calculations at the cost of timing overhead. The interval counter is scannable and its output is shifted out serially to ATE for DNL calculations. The basic difference between asynchronous or free-running PLL clocks versus synchronous data read or write limitations should be visited at this point. A low cost ATE may provide a free-running clock at frequencies in excess of 750 MHz but the synchronous data operations are limited to ≈ 25 MHz, which limits the maximum SCAN-OUT data frequency of the interval counter. The 4-bit coutner may also be useful for any future work done in the area of code-offset testing of embedded ADCs.



The ADC output is directed to the output pads and observed using a simple functional pattern. A fully-scanable scheme such as [7] would require the entire code width to be output and scanned out at-speed, which may not be feasible for a typical low cost ATE. For an n-bit code width ADC rated at foperational, the required synchronous data transfer rate is of the order of Formula TeX Source $$R_{\rm sync} = f_{\rm opr} \times W_{\rm code} + f_{\rm opr} \times W_{\rm int{-}counter} + T_{\rm overhead}$$A typical 12-bit ADC with sampling at 25 MHz with a 4 bit interval counter would result in a synchronous scan requirement of 400 MHz, significantly higher than the ≈ 25 MHz scan limit. Such a high frequency requirement in the digital block may also cause strict timing closure requirements. Running the ADC slower than the rated speed would result in production test quality issues though it may limit the data scan rates within the ATE data rate.

The hybrid scheme is shown in Fig. 4. This may be applicable to SoC or SiP systems where the ADC output is accessible either as dedicated outputs or muxed in a test mode. The overall error factor due to added noise is represented as follows: Formula TeX Source $$\epsilon_{\rm total} = \epsilon_{\rm ADC-inherent} +\epsilon_{\rm ramp-stimulus}+ \epsilon_{\rm system}$$The inherent ADC errors are not analyzed in detail in this work as their intrinsic values and probabilities can be assumed to be unchanged in the BiST scheme. Providing an internal stimulus and observing digital output nodes ensures that the εADC-inherent estimate is very close to the ADC intrinsic error. Factors εramp-stimulus and εsystem may encouter catastrophic errors in case of fabrication issues, but any errors which cause PE2 and PE3 to be one would be very easily detected by observing the ADC outputs with a functional pattern. The additional circuitry including the interval counter and scan register is digital in nature and would not be affected by any noise as long as clean clocks are used to drive the blocks and setup/hold constraints are maintained. That leaves the majority of injected noise to come out of the component εramp-stimulus, caused due to the ramp stimulus generator. The ramp generator error can be further classified into two components—waveform inherent errors in form of INL and DNL, and noise added due to the feedback mechanism. Switching noise added by the voltage feedback scheme is added to the ramp voltage peak noise. As discussed in Section I, feedback transmission gate width is optimized to ensure that the ramp peak noise present is within acceptable limits. Formula TeX Source $$N_{\rm total} = \int^{T}_0 [N_{\rm INL} + N_{\rm DNL} + N_{\rm Ramp-Slope}]$$where Formula TeX Source $$N_{\rm Ramp-Slope} = f[{\rm fab{-}corner,\ Transistor}\ W/L, C_{\rm out}]$$

Figure 3
Fig. 3. Feedback Signal Stablizing After Initialization and the Corresponding Ramp Vout.
Figure 4
Fig. 4. System Level Schematic for Hybrid BiST Scheme.
Figure 5
Fig. 5. Analog Section System Layout Stripped to MET3.

In production test, the ADC test can be a test mode which can run concurrently along with other tests due to its resource independence. An initialization signal is provided to the ramp generator by the test mode control block and the functional clocks are gated to the ADC as well as the ramp generator and interval-counter blocks. A functional pattern running on the ATE is intended to be used for observing the interval-counter output shifted serially, as well as the ADC outputs which are available as DUT outputs. The functional pattern used to test these nodes can be designed for performing Bit Error Rate (BER) type of calculations to observe INL and DNL errors by passing the recorded data to the ATE for further calculations.



We implemented the hybrid BiST scheme using a 90 nm CMOS library. Multiple SPICE level design iterations were performed to minimize the capacitor values in the ramp generator feedback path to reduce the area overhead. A smaller feedback capacitor requires a smaller trickle charge current and would reduce the fabrication area at the cost of a marginally larger output Vmax variation. A smaller capacitive load also enables smaller W/L ratios for the charging circuit. Post layout simulations were performed for the BiST scheme across process corners to confirm the SPICE simulation results. Table II contains the result summary for a total of fifteen runs performed at the three process corners. The tight distributions for ramp voltage values and CpK (Process Capability) numbers indicate robustness to process variations.

Table 2
TABLE II System Level Post Layout Simulation Results


The ADC BiST scheme proposed in this paper enables testing of ADCs on low cost ATE systems with a moderate area overhead. The hybrid nature of the methodology enables at-speed testing using a built-in stimulus while using low-end external test resources. The interval counter along with sequential analysis method can provide data required to completely characterize the ADC.


S. Dasnurkar and J. A. Abraham are with the Department of Electrical & Computer Engineering The University of Texas at Austin Austin, TX 78712 U.S.A. Email:,


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