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  • Abstract

Low-Power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs

A low power on-chip reference clock generator consisting of subthreshold MOSFET circuits is proposed. It uses a simple frequency-locked loop technique with no inductor, quartz resonator, or MEMS oscillator. Theoretical analyses and a SPICE simulation with 0.35-μm CMOS parameters showed that the clock frequency could be controlled in the frequency range of 10–1000 kHz. When operated at 170 kHz, the generator showed a temperature coefficient of 100 ppm/°C, a line sensitivity of 3%/V, and a power consumption of 20 μW. Our clock generator can be used as a reference clock for intermittent operation in power aware LSIs.



In the near future, new social information infrastructures, or “ubiquitous” network systems, with various smart-sensor devices will be developed and deployed all over the world as a part of the information age [1]. Such network systems will require a huge number of sensor LSIs that measure various physical data in our surroundings, that store and process the measured data, and that output the data on demand (see [2] for an example of such sensors). These sensor LSIs have to operate for a long time with limited energy resources such as microbatteries and energy-harvesting power sources [3]. One possible way of developing such sensor LSIs is to make them with CMOS circuits that operate in the subthreshold region of MOSFETs, i.e., a region at which the gate-source voltage of MOSFETs is lower than the threshold voltage [4], [5].

Fig. 1 shows the chip architecture of smart sensor LSIs that we are developing now. The LSI consists of sensors [2], [6], AD/DA converters, digital signal processors, memories, reference circuits [7], [8], [9], power supply circuits [10], and transceiver circuits. Microwatt operation requires that, (1) all of the circuits in the LSI are operated in the subthreshold region of MOSFETs, and that (2) the main system of the LSI is operated intermittently under the control of an on-chip reference clock circuit. Intermittent operation contributes to a drastic reduction in the power consumption of the LSI.

Figure 1
Fig. 1. Chip architecture of microwatt power-aware smart-sensor LSIs.

This paper focuses on a clock reference circuit indispensable for intermittent operation. Many reference clock circuits have been reported recently [11], [12], [13] but they are unsuitable for use in power aware LSIs because of their large power consumption (several milliwatts or more), large surface area (over 1 mm2), and use of MEMS technology incompatible with standard CMOS processes. To solve these problems, we developed a reference clock circuit that can be operated with microwatt-level power consumption, integrated in a small chip area (0.05 mm2), and fabricated using standard CMOS processes. The circuit makes use of a frequency-locked feedback loop and generates a clock frequency that is insensitive to temperature and the supply voltage.



Fig. 2 shows a block diagram of our reference clock generator. The circuit generates a reference clock using a frequency-locked loop technique. It consists of a current reference, a current comparator, a voltage-controlled oscillator (VCO), and a frequency-to-current converter (see [9] for the current reference circuit), and these circuits form a feedback loop. The current comparator detects the difference between the reference current IREF and the output current IOUT of the frequency-to-current converter and generates the output voltage VOUT proportional to the difference. The VCO accepts the output voltage VOUT and produces oscillation pulses with a frequency fREF dependent on VOUT. The frequency-to-current converter accepts the oscillation pulses and generates the output current IOUT proportional to fREF. Then the current comparator again compares currents IREF and IOUT to produce a readjusted VOUT. This feedback operation is repeated to make IOUT equal to IREF. The resultant clock frequency fREF is independent of temperature and power supply voltage.

Figure 2
Fig. 2. Block diagram of our reference clock generator.

Fig. 3 shows the configuration of our clock generator. All MOSFETs in the circuit are operated in the subthreshold region to achieve ultra-low power consumption. The following sections describe the operation of the generator in detail.

Figure 3
Fig. 3. Schematic of proposed reference clock generator.

A. Current Comparator (Block (B) in Fig. 3)

The current comparator is a common-source circuit used to detect the difference between reference current IREF and output current IOUT of the frequency-to-current converter. It generates output voltage VOUT proportional to the difference between the two. The reference current IREF (about 60 nA) that is independent of the temperature and supply voltage is provided by a subthreshold reference current circuit (not shown in the figure, see [9]).

B. Voltage Controlled Oscillator (Block (C))

The VCO consists of a current-starved ring oscillator as shown. The circuit is used for producing oscillation pulses that are dependent on output voltage VOUT of the current comparator. Oscillation frequency fREF depends on applied current Ibias and is given byFormula TeX Source $$\eqalignno{f_{REF} &= {I_{bias} \over 2mAC_{L}V_{DD}}\cr&= {I_{0} \over 2mAC_{L}V_{DD}}\exp\left({V_{DD}-V_{OUT}-V_{TH} \over\eta V_{T}}\right),\quad {\hbox{(1)}}}$$where m is the number of inverters in the oscillator, CL is a load capacitance for each inverter, A is a delay fitting parameter [14], I0 is a process dependent parameter, VT is the thermal voltage, VTH is the threshold voltage of MOSFETs, and η is the subthreshold slop factor. Oscillation frequency f depends on VOUT.

C. Frequency to Current Converter (Block (A))

The frequency-to-current converter is a current-to-voltage converter combined with a switched-capacitor resistor. The circuit is used to produce output current IREF proportional to oscillation frequency fREF of the VCO. The voltage of one end of the switched-capacitor resistor is fixed to reference voltage VREF with an operational amplifier and a MOSFET, where the reference voltage is supplied by a voltage reference circuit consisting of subthreshold MOSFETs (see [7] for this voltage reference). The switched-capacitor resistor consists of capacitor CS and two switches (sw1, sw2) driven with the oscillation pulses from the VCO, and operates as a resistor with a resistance of (CS · fREF)− 1. Therefore, output current IOUT of the frequency-to-current converter is Formula TeX Source $$I_{OUT} = f_{REF} \cdot C_{S} \cdot V_{REF}.\eqno{\hbox{(2)}}$$This current is copied into the current comparator through a current mirror. Because of the feedback operation, the circuit operates so that IOUT will be equal to IREF, and consequently, oscillation frequency fREF will beFormula TeX Source $$f_{REF} = {I_{REF} \over C_{S} \cdot V_{REF}}.\eqno {\hbox{(3)}}$$Because IREF and VREF are independent of temperature, output frequency fREF is also insensitive to temperature.

This way, a constant reference clock with little dependence on temperature can be obtained.



We confirmed the operation of the circuit using a SPICE simulation with a SPECTRE level 53 model and a parameter set of a 0.35-μm 2P4M-standard CMOS process. The supply voltage was set to 3 V (the nominal voltage of lithium-ion batteries). Fig. 4 shows the entire construction of our clock reference generator. The VCO consists of seven current-starved inverters connected in a ring. A non-overlapping clock generator was used to prevent switches sw1 and sw2 from being turned on simultaneously. Reference current IREF and reference voltage VREF were set to 60 nA and 0.8 V. Capacitors CB and CC remove high frequency noise resulting from the switching operation. The results of the simulation are shown in the following.

Figure 4
Fig. 4. Entire circuit of reference clock generator. All subcircuits are operated in the subthreshold region except for the buffer circuit and non-overlapping clock generator.

The output frequency was adjusted by reference current IREF, and we found oscillation in the 10–1000 kHz frequency range. Fig. 5 shows an example with a frequency of 170 kHz. The duty ratio of the waveforms (P) and (Q) as shown in Fig. 4 was about 50%. Fig. 6 shows oscillation frequency fREF as a function of temperature from −20 to 80°C with different supply voltages. The variation in frequency was 1.7 kHz, and the temperature coefficient was 100 ppm/°C for 3-V supply voltage. The circuit operated correctly with a supply voltage higher than 2.2 V. The line sensitivity was 3%/V for a 2.2–3.3 V supply voltage. A constant clock frequency that is insensitive to the temperature and power supply was obtained. The lower limit of the supply voltage was reduced to less than 2.2 V using an operational amplifier instead of the cascode current mirrors used in this example. Fig. 7 shows the supply current as a function of temperature with supply voltage VDD as a parameter. The supply current with 3-V power supply was about 6.8 μA. The temperature coefficient of the supply current was 0.02%/°C for VDD = 2.2 V, 0.08%/°C for 2.5 V, and 0.15%/°C for 3 V.

Figure 5
Fig. 5. Output waveform of circuit at room temperature. The duty ratio of the waveform was about 50%.
Figure 6
Fig. 6. Oscillation frequency fREF as a function of temperature.
Figure 7
Fig. 7. Supply current as a function of temperature.

To examine the tolerance to device-parameter variation, we performed a corner analysis, using parameters provided by a manufacturer. The worst corners of nMOS and pMOS transistors (S: slow, T: typical, and F: fast) were taken into consideration. Fig. 8 shows output frequency fREF for five sets of process corner conditions. The value of fREF changed depending on the set of process corners. This occurred because the reference current IREF and reference voltage VREF depend on process variation. However, the reference clock fREF was independent of temperature in each process corner condition. Fig. 9 shows the chip layout of the circuit designed with 0.35-μm, standard CMOS process parameters. The chip area was 0.05 mm2 ( = 220 μm × 230 μ m), and the power consumption was 20 μW for a 3-V supply voltage. Table I summarizes the performance of our clock generator.

Figure 8
Fig. 8. Output frequency fREF simulated with corner analysis. Process corners of nMOS and pMOS transistors were taken into consideration.
Figure 9
Fig. 9. Layout pattern of reference clock generator (current reference and voltage reference are not shown.)
Table 1
TABLE I Performance summary


Our clock generator is compatible with standard CMOS technology and operates with ultra-low power consumption. It can be used as an on-chip timer to control intermittent operation of power aware LSIs as described at the beginning of this paper. The clock generator can also be used as a timer that notifies regular intervals to check and inspect systems. Another possible application is with accumulating sensors. Our clock generator oscillates with a frequency proportional to the reference current, so combining the generator with transducers can construct accumulating sensors that measure the integration of temperature, sunshine, and other environmental parameters. We are now developing various intelligent sensor LSIs that use our on-chip clock generators.


This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc.


K. Ueno, T. Asai, and Y. Amemiya are with the Department of Electrical Engineering, Hokkaido University, Sapporo 060-0814 Japan Tel: +81-11-706-7149, Fax: +81-11-706-7890 E-mail:


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Ken Ueno

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Tetsuya Asai

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Yoshihito Amemiya

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