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  • Abstract

A Fast-Lock Synchronous Multi-Phase Clock Generator Based on a Time-to-Digital Converter

An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine delay measurement and compensation. The proposed clock generator was designed in a 0.18 um CMOS technology. It operates over a wide frequency range from 400 MHz to 1.22 GHz and consumes 34 mW at 1.22 GHz.

SECTION I

INTRODUCTION

Multi-phase clocks are widely used in many applications such as microprocessors and double date rate (DDR) and quadrate date rate (QDR) memories to achieve a higher operation frequency than that of the main internal clock. To achieve high-speed interfaces, a multi-phase clock generator is required to obtain a low power consumption, a fast-locking time, wide frequency range, and clock synchronization. Recently, several multi-phase clock generators have been proposed for high-speed interfaces [1], [2], [3], [4], [5], [6]. The digital clock generators in [1], [2], [3] achieved a small area and fast-locking time by using a time-to-digital converter (TDC). However, the clock generators need a clock synchronous circuit, such as a delay-locked loop (DLL) or synchronous mirror delay (SMD), so that they suffer from the trade-off between the phase resolution and the range of operating frequency. In order to achieve high resolution and clock synchronization, DLL-based multi-phase clock generators were proposed in [4], [5], [6]. However, DLL-based clock generators occupy a large area due to their use of two independent DLL-based circuits for multi-phase generation and clock synchronization and are not suitable for low-voltage and fast-lock operation. All-digital SMD circuits are also employed for fast-lock clock synchronization [7], [8]. However, SMD circuits have difficulties when it comes to multi-phase clock generation and have a low resolution and large area.

In this paper, a clock generator is proposed that has a small area, fast-lock time, high resolution and clock synchronization, which are achieved by using an open-loop, all-digital TDC with a de-skewing circuit. The organization of this paper is as follows. In Section II, the overall architecture and individual building blocks of the proposed synchronous multi-phase clock generator are described. Section III describes the simulation results and our conclusions are drawn in Section IV.

Figure 1
Fig. 1. Architecture of the proposed synchronous multi-phase clock generator.
SECTION II

PROPOSED MULTI-PHASE CLOCK GENERATER

The architecture of the proposed synchronous multi-phase clock generator is shown in Fig. 1. The clock generator consists of a TDC, sampling clock selector, control pulse generator, code controller and de-skewing circuit. For fast-locking clock synchronization and multi-phase generation, the clock generator uses a TDC which measures the period of the input clock and the replica delay. The TDC comprises a delay line, a high-to-low transition detector and a quantizer. The delay line is divided into 32 equal delay cells to achieve a wide frequency range and each of the delay stages feeds its corresponding delayed clock into the multiplexer. Since all of the delay cells comprise two static inverters and have the same loading capacitance, they change the delay to the same extent. In order to measure the delay, each positive edge-triggered D-flip/flop of the quantizer compares the sampling clock (sclk) with the output clocks (d‹1:n›) of the delay line. The sampling clock selector passes one of two delay paths, viz. the replica delay path or non-delay path. The high-to-low transition detector senses the number of delay cells which have measured delay information. The measured delay codes are used by the code controller to generate 5 bit-coarse and 3 bit-fine codes for clock synchronization and multi-phase generation. The multiplexer outputs four-phase clocks according to the coarse codes of the code controller which are subsequently finely tuned by the de-skewing circuit.

A. Fast-Locking Clock Synchronization

The proposed clock generator achieves fast-locking clock synchronization by using the TDC, and the concept of the clock synchronization is described in Fig. 2. When the start signal is enabled, the sampling clock selector makes the input clock pass through the replica delay path. Then, the TDC measures the amount of delay by subtracting multiple periods of the input clock from the replica delay, as described by (1) and also shown as delay(a) in Fig. 2.Formula TeX Source $${\rm Delay}(a) = {\rm Treplica} - N ^\ast Tclk,\eqno{\hbox{(1)}}$$where Treplica indicates the replica delay including the input and output buffer delays and N and Tclk represent the natural number and a period of the input clock, respectively. The code controller stores the delay obtained by (1).

Figure 2
Fig. 2. Concept of clock synchronization.

The TDC also measures one period of the input clock which passes through the non-delay path, as represented by delay(b) in Fig. 2. The amount of DLL delay to be compensated to achieve clock synchronization with the reference clock is obtained by subtracting delay(a) from one period of the input clock, as described by (2).Formula TeX Source $${\rm DLL\ delay} = {\rm delay}(b) - {\rm delay}(a)\eqno{\hbox{(2)}}$$

The TDC spends 16 cycles of the input clock to measure the coarse and fine delays of the replica delay and one period, respectively. As a result, the clock synchronization of the proposed clock generator can be realized within 45 cycles of the input clock by adding the DLL delay to the input and output buffer delays.

B. Fine Delay Measurement

In general, TDCs have a fast-locking time but suffer from the trade-off between the phase resolution and the range of operating frequency. If the unit delay of the TDC is reduced to achieve a high resolution, its overall power consumption increases, because a larger number of unit delay cells are required to satisfy the same frequency range. Therefore, a high resolution, wide frequency range and low-power TDC is required in a high-speed interface. In the proposed clock generator, the phase mixer of the sampling clock selector is implemented to achieve high resolution while simultaneously using the same delay line as that shown in Fig. 3. The sampling clock selector consists of a replica delay, a MUX, a unit delay, and a phase mixer. The replica delay includes the input and output buffer delays. The MUX passes one of the two delay paths into the phase mixer according to the control signal of the control pulse generator. The unit delay uses the same one as the delay line of the TDC. For fast-lock, fine delay measurement, the TDC adopts the binary search method.

Figure 3
Fig. 3. Block diagram of the sampling clock selector.

Fig. 4 shows the binary search method for fine delay measurement. In the first step, the TDC compares the input clock (inclk) with the output clocks (d‹ 1:32›) of the delay line and then stores the output codes (tdc_out ‹1:32›), which become the coarse codes, in the 5 b-latch of the code controller. Next, in the second step, the TDC compares inclk delayed by a + 0.5 unit delay (UD) with d‹ 1:32 ›. If the output codes of the TDC are equal to the codes stored in the 5 b-latch, the phase mixer causes inclk to be delayed by a further +0.25 UD. Otherwise, it reduces the delay by 0.25 UD. As mentioned above, in the TDC, the inclk is shifted back and forth to search for the transition edge precisely by adding or subtracting the binary-weighted ratio of the UD. The TDC continues these operations while performing the 4 step-search for fine delay measurement. The state machine of the code controller catches the fine codes with the output transition of the TDC.

Figure 4
Fig. 4. Binary search method for fine delay measurement.

C. Multi-Phase Generation With De-Skewing Circuit

The delay codes generated by the TDC are converted into coarse and fine codes in the code controller, which consists of a code generator and a code calculator. The block diagram of the code controller is shown in Fig. 5. The code generator encodes the 32 bit output codes of the TDC into 5 bit binary codes which are to be stored in a 5 bit latch. After the measurement of the fine delay, the 5 b-latch feeds the 5 bit binary codes as the coarse code into the code calculator to generate synchronous codes and four-phase selection codes. In order to define the fine codes, the digital comparator compares the stored codes with the binary search codes of the phase mixer and, then, the state machine senses the transition of the binary search codes according to the compared value of the digital comparator. The state machine stores the 3 bit fine codes and then feeds them into the code calculator.

Figure 5
Fig. 5. Block diagram of code controller.

The code calculator consists of two 8 b-latches, three digital dividers, and adders. It generates coarse and fine codes for clock synchronization and multi-phase generation. The replica delay code is stored in an 8 b-latch when Rclk is enabled and the information about one period of the input clock is stored in another 8 b-latch when Pclk is enabled. The synchronization code can be generated by subtracting the replica delay code and one-period code. Also, the codes for Φ90, Φ180 and Φ270 can be generated through the operation of clock synchronization and one-period code divided by 1/4, 1/2 and 3/4. Each coarse code selects the four-phase clocks by controlling the multiplex and each fine code calibrates the phase resolution of the multi-phase clocks finitely by controlling the de-skewing circuit.

Fig. 6 shows the methodologies used generating the four phase clocks of the conventional and proposed clock generators. The conventional clock generator detects one period of the input clock (Φ0) and then selects the other three-phase clocks (Φ90, Φ180 and Φ270) of the multiphase clocks of the delay line [2]. Because the maximum phase error of the capture zone in the conventional clock generator is ± τ/2, the maximum phase errors of Φ90, Φ180 and Φ270 are ± τ/8, ± τ/4 and ± 3 τ/8, respectively. The proposed clock generator uses the same methodology as the conventional one, however, it has a capture zone of ± τ/8, which is a quarter of the conventional one, because of the binary-searching phase mixer of the sampling clock selector used for fine delay measurement. Therefore, the maximum phase errors of Φ90, Φ180 and Φ270 are ± τ/32, ± τ/16 and ± 3 τ/32, respectively. The reduced capture zone is realized by the de-skewing circuit. Fig. 7 shows the block diagram of the de-skewing circuit which uses the same phase mixer and unit delay cell as the sampling clock selector. The fine codes of the binary-searching phase mixer are fed into the de-skewing circuit to improve the phase resolution of the multi-phase clocks.

Figure 6
Fig. 6. Methodologies used for generating four phase clocks of conventional (a) and proposed (b) clock generators.
Figure 7
Fig. 7. Block diagram of de-skewing circuit.
SECTION III

SIMULATION RESULT

The proposed multi-phase clock generator is designed in a 0.18 um CMOS technology. Fig. 8 shows the simulated result of the proposed clock generator. When the supply voltage is 1.8 V and the input frequency is 1.22 GHz, the phase error between the reference and output clocks is + 4.6 ps and the phase differences between the adjacent phases of the four-phased clock (Φ0 vs. Φ90, Φ90 vs. Φ180, Φ180 vs. Φ270 and Φ270 vs. Φ0) are 201.4 ps, 209.2 ps, 200.6 ps and 209.2 ps, respectively. The ideal phase difference at 1.22 GHz is 205 ps. The proposed clock generator operates over a wide frequency range, from 400 MHz to 1.22 GHz, and consumes 34 mW at 1.22 GHz with a supply voltage of 1.8 V. A comparison between this work and a previously reported multi-phase clock generator is shown in Table I. In this table, the main characteristics, such as the alignments with the input clock, phase error, power consumption, locking time and frequency range, are compared.

Figure 8
Fig. 8. Simulation result of the proposed synchronous multi-phase clock generator.
Table 1
TABLE I Performance comparison
SECTION IV

CONCLUSION

In this paper, an all-digital multi-phase clock generator is presented. The proposed clock generator can generate four-phase clocks as well as synchronize with the reference clock within 45 cycles by using a TDC. Furthermore, by using a binary search scheme for fine delay measurement, the clock generator improves the phase resolution without reducing the unit delay of the delay cell increasing the number of delay cells of the delay line. In order to tune the fine delay, a deskewing circuit is implemented. The proposed clock generator is designed with a 0.18 um CMOS technology. The clock generator operates over a wide frequency range from 400 MHz to 1.22 GHz and achieves a phase resolution of less than 7.5 ps. It consumes 34 mW at 1.22 GHz with a supply voltage of 1.8 V.

Footnotes

D. Shin, J. Koo, W.-J. Yun, Y. J. Choi are with Graphics Memory Design Team, Hynix Semiconductor, Icheon, Korea E-mail: dongsuk1.shin@hynix.com

C. Kim is with the Department of Electronics and Computer Engineering, Korea University, Seoul, Korea

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Authors

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Dongsuk Shin

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Jabeom Koo

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Won-Joo Yun

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Young Jung Choi

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Chulwoo Kim

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