Simulation of the variability in microelectronic capacitors having polycrystalline dielectrics

The scaling down of on-chip microelectronic capacitors presents a considerable challenge for future microelectronic devices. High-permittivity polycrystalline dielectrics such as Ta/sub 2/O/sub 5/, SrTiO/sub 3/ (STO), or (Ba, Sr)TiO/sub 3/ (BSTO), have been considered as a potential replacement for conventional amorphous SiO/sub 2/ and SiN/sub x/. The polycrystalline microstructure of these materials may lead to capacitor-to-capacitor variations in charge storage capacity and charge retention. In this letter, a Monte Carlo simulation is used to assess these variations. Results show that as the average crystalline grain size becomes greater than 1% of the capacitor size, variations of 10% in capacitance and between 3-150% in leakage should be expected.