A polynomial division pipelined architecture for CRC error detecting codes

Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundancy Checking). However, the evolution towards increasing data rates increases the need for more and more sophisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bit).