A 3.68 aFrms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS

This article describes a fourth-order continuous-time (CT) bandpass (BP)-
$\Delta \Sigma $
capacitance-to-digital converter (CDC) for full-CMOS sensors having ultrahigh-resolution and high-energy efficiency. To improve the resolution of
$\Delta \Sigma $
CDC, a CT instead of a discrete-time (DT) operation is employed to overcome a thermal noise limitation. Moreover, a BP-
$\Delta \Sigma $
modulator is used to save power consumption compared to lowpass (LP) or highpass (HP)-
$\Delta \Sigma $
Ms. In addition, a charge-domain digital-to-analog converter (DAC) at the input stage of the
$\Delta \Sigma M$
is proposed for low thermal noise and simplicity. An inverter-based amplifier is used for low power consumption and gain boosting circuit is added to increase dc gain of the amplifier. Implemented in
$0.18~\mu \text{m}$
CMOS, the proposed CDC achieves a ultrahigh-resolution of 3.68 aFrms and the highest Schreier figure-of-merit (FoMS) of 183 dB which is 3.3 dB improvement over the recent state-of-the-art CDCs.