Implementation of the Silicon Track Card (STC) as a system-on-a-programmable-chip (SOPC)

The current paper details implementation of the Silicon Track Card (STC) card using a programmable logic device (PLD) for the DZERO (D0) upgrade currently underway at Fermi National Accelerator Laboratory (FNAL), Batavia, Illinois. This project is a collaboration between researchers from the Department of Electrical and Computer Engineering, Florida Agricultural and Mechanical University-Florida State University (FAMU-FSU) College of Engineering, researchers from High Energy Physics (HEP), Florida State University and High Energy Physics, Boston University (BU). The STC project is based on the specifications provided by the researchers at BU and a preliminary STC module designed using the Very High Speed Integrated Circuit (VHSIC) hardware description language (VHDL). The upgraded STC has a modified memory map and a new Level 3 (L3) buffer module. Traditionally discrete components of memory and processor cores were externally connected, while current implementation aims at configuring them into a single device, thus increasing general system performance by decreasing board area and time delays associated with transmission lines on the printed circuit board. The STC targets the Advanced Programmable Embedded MatriX (APEX) family of PLDs developed by Altera Corporation.