Buffer design of nonblocking ATM switch for bursty traffic

In any practical ATM switch design, a proper dimensioning of buffer size B can guarantee, a specified cell loss percentage requirement, for given traffic type. A 4/spl times/4 ATM switch with parallel iterative matching scheduling algorithm has been simulated to study the effect of input buffer size on mean cell delay through the switch and cell loss percentage in the switch. Arriving traffic on all input ports is taken to be bursty in nature with a given average burst length. Mean cell delay and cell loss percentage for various input buffer sizes were obtained as the output of simulations. Analytical models for these quantities have been developed to aid in the buffer design for the practical ATM switch.