Memory power models for multilevel power estimation and optimization

Storage cost is a major factor in the total power consumption of digital signal processing circuits. Power models for on-chip memories are consequently an important ingredient in power aware design flows for estimation and optimization. Unfortunately, exact memory-modeling techniques are not widely applied in practice. This is mainly due to the vendors' need for intellectual property protection (IPP), the ill fit into vendors' design cycles and the significant overhead in time and manpower involved. To bridge the gap, between vendors and designers, we suggest an automatic black box modeling approach. It is based on nonlinear regression that combines all desired properties: accuracy, flexibility, speed, low overhead, a good fit into the vendors' design cycle, IP protection, plus a mathematical form that is well suited for optimization.