Electronic testing for SOC designers

Summary form only given. The presentation is divided into three parts. Part I contains definition of test and its motivation, test process and automatic test equipment (ATE), test economics and product quality, and fault modeling. Part II includes logic and fault simulation, testability measures, combinational and sequential ATPG, memory test, DSP-based analog test, model-based analog test, delay test, and IDDQ test. Part III covers scan design, built-in self-test (BIST), boundary scan, analog test bus, system test and testing of core-based designs.