i/sub DDT/ test methodologies for very deep sub-micron CMOS circuits

In this paper, we investigate three i/sub DDT/-based test methodologies, Double Threshold i/sub DDT/, Delta i/sub DDT/, and Delayed i/sub DDT/, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure.