Reducing test power during test using programmable scan chain disable

A novel method for reducing average power during scan testing is presented. The flip-flops of a full-scan module. are assigned to scan chains and the vectors are reordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from taking part in scan shifting, and hence reduces switching activity in the circuit. Moreover, disabling the clock also reduces power dissipation in the clock tree, which can be a major source of power consumption. The hardware modification that is required to implement this approach is to add the capability for the tester to gate the clock for any subset of the scan chains in the core.