A 3 V /spl Delta//spl Sigma/ receiver with sampling rate enhancement for CDMA baseband processor IC

A 3V /spl Delta//spl Sigma/ CDMA baseband receiver has been designed which has a 4th-order single-loop modulator that enhances the effective sampling rate without increasing the actual rate, achieves 62 dB DR (dynamic range), consumes 22 mW, and occupies 1.3 mm/sup 2/ in 0.25 /spl mu/m CMOS. This receiver is part of an 8 M transistor 10.5/spl times/10.5 mm chip which integrates receiver, transmitter, voice codec, 10 bit ADC and DAC, PLL, 32 kHz oscillator, two DSPs, memory, and ARM.