Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N/sub 2/O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22/spl deg/C to 90/spl deg/C) has been investigated. The effect of nitrogen annealing (20 min) at 400/spl deg/C on high temperature stress-induced interface traps was also studied.