Characterization of Oxide Trapping in SiC MOSFETs Under Positive Gate Bias

SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability (
${\mathrm {V}}_{\mathrm {TH}}$
hysteresis and
$\Delta{\mathrm {V}}_{\mathrm {TH}}$
) and on-resistance degradation (
$\Delta{\mathrm {R}}_{\mathrm {ON}}$
) are used to characterize oxide trapping. Although the observation method is different, it can be found that the
${\mathrm {V}}_{\mathrm {TH}}$
instability and
${\mathrm {R}}_{\mathrm {ON}}$
degradation increase linearly with logarithmic time over a wide time range from
$100~\mu{\mathrm {s}}$
to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is
$3.8\times 10^{12}$
cm−2
$\cdot$
eV−1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter
$\gamma$
from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhenius plot.