A silicon bipolar decision circuit operating up to 15 Gb/s

A master-slave D-flip-flop (MS-D-FF) IC usable as a decision circuit has been realized in an advanced self-aligned silicon bipolar technology using 0.8- mu m lithography. The circuit has been operated up to 15 Gb/s (at a clock phase margin (CPM) of 180 degrees C) with a 5-V supply voltage. The data rate of 15 Gb/s is not the limit of this decision circuit if CPM values lower than 180 degrees can be tolerated, or if input voltage swings above 400 mV/sub p-p/ are available.<
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