A High PAE Stacked K-band Power Amplifier Using π-Phase Compensation Technique

A three-tunable low-pass π-phase compensator technique is proposed and employed in a K-band CMOS power amplifier (PA) to solve the phase shift problem at intermediate nodes of stacked transistor configurations (STCs). Also, it reduces the effects of harmonic signals that in turns, enhances the overall power added efficiency (PAE) of the PA. The PA consists of two stages i.e. driver and main stages, designed using 2-STCs in 180-nm CMOS technology. The fabricated PA achieved a power gain of 12.8 dB at 23 GHz, a maximum PAE of 18.3%, an output power of 1 dB compression point $\left(\mathrm{P}_{1 \mathrm{~dB}}\right)$ of 14.1 1 dBm, and saturated output power $\left(\mathrm{P}_{\text {sat }}\right)$ of 16.0 dBm while it consumes chip area of 0.604 mm² including pads.