Prediction of Power Supply Induced Jitter With PDN Design Parameters

This article proposes a method to predict power supply induced jitter (PSIJ) at the inverter chain buffer output with the design parameters of power distribution network (PDN). The PDN is assumed to contain multiple decoupling capacitors with sufficiently different values for each branch. The relationship between PSIJ and PDN design parameters is derived analytically by convoluting the time-domain voltage ripple with the buffer time-domain PSIJ sensitivity, given the triangular noise current information. The analytical formula is validated through measurement by using an in-house designed CMOS buffer circuit and a controllable aggressor circuit based on 180 nm technology. The buffer output PSIJ under the operation of the aggressor circuit and the corresponding switching noise current are characterized. The
R–L–C
design parameters of PDN are extracted through impedance measurement. With the PDN parameters, the output jitter is calculated with the derived formulation. Compared with the measurements, the prediction error of the proposed method is within 8.1% when the voltage ripple amplitude is no larger than 10% of the supply voltage.