A 12-bit integrated analog front end for broadband wireline networks

An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit data path, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, a tuned analog 4-pole filter, a 12-b analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. Filter tuning using switched-capacitor arrays occurs in the background, with no effect on signal reception. The transmit data path contains digital interpolation filters and a 12-b digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35-/spl mu/m CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk.