Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities.