A new test structure for short and long distance mismatch characterization of submicron MOS transistors

A new test structure for the characterization of statistical variations of the parameters of submicron MOS devices is presented in this work. The structure has been designed for the estimation of mismatch parameters as a function of the device dimensions and positions in the die. Low area consumption and a reduced measurement time required for the complete mismatch characterization are the main objective of the design. The test structure consisting of about 6000 MOSFETs has been used for mismatch characterization of a 0.18 /spl mu/m CMOS technology.