A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion Cancelation Achieving 6.3 fJ/conv-step

A 1-GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog-to-digital converter (ADC) is presented. It consists of three stages (4b-4b-6b) with two one-bit interstage redundancies implemented. A novel harmonic-injecting cross-coupled pair (HXCP) is proposed in an inverter-based residual amplifier (RA) as a critical part of the presented ADC. By implementing the HXCP, the linearity of the RA is effectively improved and meanwhile the gain of the RA is boosted to about 8. The HXCP is designed to be tunable to enhance its robustness against PVT variation. The prototype single-channel ADC was fabricated in 28-nm CMOS process and achieves
$\mathbf {\mathrm { > }}60$
-dB SNDR and
$\mathbf {\mathrm { > }}70$
-dB SFDR up to 320 MHz, corresponding to a 6.3 fJ/conv-step FoM
_w
and 170.5-dB FoM
_s
.