All digital timing recovery and programmable gain amplifier controller for VDSL transmission

We discuss all digital timing recovery and programmable gain amplifier (PGA) controller for carrierless amplitude and phase (CAP) modulation based very high-rate digital subscriber line (VDSL) system. We first investigate statistical properties of timing jitter of symbol timing recovery circuit for VDSL application. Analytical expressions of the timing jitter for an envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec. We also present simulation results for PGA controller and blind equalization, which have been incorporated to implement CAP-based VDSL transmission system.