Adiabatic NP-domino circuits

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuits adopting AC power supply. First, we discuss the algebraic expressions and the corresponding properties of clocked signals. Then, based on summing up the traditional domino circuit design, the design of NP-domino circuits adopting power-clock is proposed in this paper. We carry out PSPICE simulations for the four-stage clocked NP-domino circuit by using sinusoidal power-clock, and demonstrate that the circuit has correct logic function and the working characteristic of energy recovery.