A 3.3-V, 2-GHz CMOS low noise amplifier

A CMOS low noise amplifier is designed based on a narrowband LC-tuned cascode topology. With a standard 0.6 micron CMOS technology, this technique is applied to design a 3.3 V LNA operating at 2 GHz for IMT2000 band application. On-chip inductors have been used. Simulation results show that the LNA is featured with a gain of 18 dB, noise figure of 2.3 dB, IIP3 of -4.9 dBm, power dissipation of 33.9 mW, and well-matched inputs.