A 1 GHz analog multiplier with shunt-peaked LNA core

A 1 GHz analog multiplier with a supply of 1.2 V is implemented with a 0.6 micron DPDM standard CMOS technology of CSMC, China. With a shunt-peaked, low noise amplifier (LNA) core, the proposed multiplier features with IIP3 of 6.3 dBm (for mixer application), conversion gain of 10 dB and noise figure of 18 dB with a power consumption of 22 mW. Several design techniques have been adopted to achieve the target of low noise, low power and high speed. This multiplier can be used as the basic element of a RF mixer.