A scalable test mechanism and its optimization for test access to embedded cores

In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE also is a hierarchical structure. It is easy to build a hierarchical test access mechanism.