A high performance MAC design using proposed low power IP-cells

In this paper, a study is presented on High Speed (HS) and 59 mW Low Power (LP) 16/spl times/16 MAC performance of new XOR-based circuits using transmission gate (TG) logic implemented in 0.25 /spl mu/m CMOS SLP/5LM technology. It is shown that our proposed MAC results in better performance than other published MACs due to the lack of DC leakage currents for low power and the elimination of unnecessary switching activities with latches before and after multipliers for high speed.