Folding pipeline architecture based on the least-energy algorithm for high level synthesis

Pipeline architecture is very important in high level design and synthesis of digital circuits, especially for datapath design. The paper focuses on the folding pipeline architecture, presenting a new transform method for resources allocation with timing constraints. A least-energy folding and cycling schedule algorithm is proposed for synthesis, and a pipelined architecture based on a butterfly net is realized, which has benefits for interconnection design in deep-submicron technology.