CEP: a clock-driven ECO placement algorithm for standard-cell layout

Incremental placement or ECO (engineer change order) placement is a new field in VLSI layout to meet the demand of high performance design. In this paper, a novel clock-driven ECO placement algorithm, CEP, is presented for standard cell layout design. It considers clock skew information in the placement stage, modifies the positions of cells locally to make better preparation for the clock routing. Experimental results show that CEP can improve the skew bounds distribution evidently, with little influence on other performance aspects.