Synchronization circuit performance

Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures (MTBF) is given. These effects can be explained by extending the existing theory to take account of initial offsets, and we propose a new, more accurate, formula. Synchronizer performance depends on achieving a high reliability of synchronization together with a short time. We show that commonly used circuits, such as the jamb latch, do not produce the best compromise for very high reliability applications, and that a better circuit can be designed. In order to confirm that thermal noise does not influence the MTBF against synchronization-time relationship, we have devised an experiment to measure noise in an integrated CMOS bistable circuit. We show that the noise exhibits a Gaussian distribution, and is close to the value expected from thermal agitation.