Design of 10 GHz, 2.6 mW frequency divider in 0.25 /spl mu/m CMOS

This paper describes the design of high speed, low power-dissipation frequency divider. The circuit has wide applications in high-speed communication systems, especially in clock recovery and frequency synthesis. Since frequency divider is one of the key parts in the frequency synthesis, divider's speed limits the precision and the frequency of the frequency synthesis. In the paper, a frequency divider configured as master-slave flip-flop based on RAM cell is presented. Using TSMC 0.25um CMOS SPICE parameters, the divider circuit is simulated with HSPICE and get such results: while operating at 10 GHz with the 2V supply voltage, it dissipates only 2.6mW.