Multilevel interconnect technologies in SoC and SiP for 100-nm node and beyond

Since technology trends for interconnects differ from those of transistors, in that there is reverse scaling with regard to the trend towards increased integration and speed, interconnect levels increased due to two-dimensional (horizontal) limits. A maximum number of Cu interconnect levels is anticipated for 100-nm generation logic devices that enter the giga-hertz band. While Cu/low-k multilevel interconnect technology has become established, reducing wiring capacitance for a reduction in delay time, the inadequacy of the relationship between the Cu interconnect process and low-k material characteristics has been focused upon.. In this paper, the current status and issues of Cu interconnects in system LSIs and Cu/low-k multilevel interconnects for 100-nm are described.