Codesign for Generation of Large Random Sequences on Zynq FPGA

This work presents two codesign implementations of a true random number generation mechanism. Physical components provided by the programmable logic of FPGA are used for true random seed generation. The seed conditioning and generation of the large sequences were implemented using the block cipher Advanced Encryption Standard (AES) implemented on the Cortex-A9 processor (embedded in the Zynq FPGA) or specific AESNI instructions in modern processors. Our implementations use less than 10% of the available resources on the target FPGAs and pass all the National Institute of Standards and Technology (NIST) tests for random generators.