Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network

This paper presents hardware-friendly algorithm for Gini-index (GI) cooperative-spectrum-sensing (CSS) algorithm for the data-fusion based cooperative cognitive-radio network. It simplifies the complex computations of sample-covariance-matrix (SCM) elements and test-statistics value of the conventional GI-based CSS algorithm. It delivers excellent detection performance under the realistic scenario of non-uniform dynamical noise and signal-power. Based on GI-based CSS algorithm, three different VLSI architectures are proposed for the cooperative spectrum sensor (CSR): CSR-VLAR1, CSR-VLAR2, and CSR-VLAR3. Here, CSR-VLAR1 is the first-time reported CSR-architecture for the conventional GI-based CSS algorithm. Subsequently, CSR-VLAR2 represents hardware-architecture of the proposed hardware-friendly GI-based CSS algorithm. Eventually, additional architectural optimization has been applied to CSR-VLAR2 that is transformed into the most hardware-efficient VLSI-architecture of CSR, referred as CSR-VLAR3, which is ASIC chip-fabricated in UMC 130 nm-CMOS technology node. Furthermore, both CSR-VLAR1 and CSR-VLAR2 are synthesized and post-layout simulated in the same technology node. Our ASIC-chip of CSR-VLAR3 occupies 0.35 mm
²
of core-area and consumes 8.31 mW of total power at 88.8 MHz of maximum clock frequency, when the supply voltage is 1.2 V. Our CSR ASIC-chip has been functionally verified with the aid of real-world signals, using USRPs and FPGAs based test-setup of cooperative cognitive-radio network. Measured results of our design are compared with reported implementations where the proposed CSR is
$4.52\times $
hardware-efficient and
$2.8\times $
power-efficient than the state-of-the-art CSR-implementations. Thus, our work addresses the key challenge of designing hardware-efficient CSR that delivers excellent detection performance in the real-world scenario.