A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a 7T Dynamic Residue Amplifier

This letter presents a 3-stage pipelined successive-approximation-resister (SAR) analog-to-digital converter (ADC) using a seven transistor-dynamic residue amplifier (7T-DA) for kickback noise cancelation. Thanks to the pipeline structure, the input capacitance is only 16 fF, achieving an effective resolution bandwidth (ERBW) of 2 GHz. The gain sensitivity to the temperature of the dynamic amplifier is reduced by an on-chip low-dropout voltage regulator (LDO) and a pulse generator. Fabricated in the 28-nm CMOS process, the prototype ADC running at 800 MS/s achieves a peak SNDR of 42.7 dB and SFDR of 52.0 dB at Nyquist input. It also achieves SNDR of 38.9 dB and SFDR of 49.9 dB at a 2-GHz input. The total power consumption of ADC is 1.55 mW, which corresponds to the Waldon figure of merit of 17.4 fJ/conv step and Schreier FoM of 156.8 dB, respectively.