Achieving power efficiency through minimum cycle time in digital signal processor design

Fast microprocessors exploit instruction level parallelism and high clock frequency. On the other hand, power dissipation is reduced by lowering the supply voltage and consequently increasing the clock cycle time. This paper presents a DSP architecture which targets a simple, low-cost and ultra-high frequency implementation, showing that this choice leads to high power efficiency in terms of dissipation with constrained performance. The design reduces the cycle time by a combination of instruction set as well as microarchitecture design choices. The architecture performance is extensively evaluated by means of instruction level simulation of standard DSP benchmarks and cycle time estimation. A theoretical analysis of the power efficiency is also provided.