Novel Accumulation Mode Superjunction Device With Extended Superjunction Gate

In this article, accumulation mode (AC) is used for superjunction (SJ) vertical double-diffused metal–oxide–semiconductor (VDMOS) and a new SJ VDMOS with extended SJ (ESJ) gate is proposed. The AC ESJ VDMOS is proposed by introducing p pillar and n pillar between the electrodes of gate and drain. In the
$\mathrm{\scriptscriptstyle ON}$
-state, the electron accumulation layer and the inversion layer are formed in the drift region, which widens the current path and reduces the specific
$\mathrm{\scriptscriptstyle ON}$
-resistance (
${R}_{\mathrm{\scriptscriptstyle ON},\text {sp}}$
). In the
$\mathrm{\scriptscriptstyle OFF}$
-state, the ESJ modulates the surface electric field of the drift region, which enhances the breakdown voltage (BV). Simulation results indicate that with the drift region of
$19~{\mu } \text{m}$
,
${R}_{\mathrm{\scriptscriptstyle ON},\text {sp}}$
of AC ESJ VDMOS can be reduced by 71.1% (0.63
$\text{m}{\Omega } \cdot $
cm
²
) compared with the conventional SJ VDMOS (2.18
$\text{m}{\Omega } \cdot $
cm
²
), and the BV is increased by 12.3% from 349.2 to 392.2 V. Compared with the p-type ESJ SJ VDMOS, the BV of AC ESJ VDMOS is increased by 16.23% from 617.2 to 717.4 V under the drift region of
$39~\mu \text{m}$
.