Split-path skewed (SPS) CMOS buffer for high performance and low power applications

Splitting a regular multistage CMOS buffer into two separate paths, and then skewing each path in opposite directions to achieve faster delay leads to a new, high-speed, split-path skewed (SPS) CMOS buffer. The two skewed paths are statically merged in the final stage such that the short-circuit current is eliminated without tri-stating the output. The proposed circuit is simulated for various skew values in a 0.18 /spl mu/m CMOS technology for a 1.8 V supply voltage. The SPICE simulation results validate the fast operation of the proposed buffer and show that the energy delay product is always reduced and, for a skew value of four, the delay with respect to a regular tapered buffer design is reduced by 28% to 34%.