Analysis of power/ground-plane EMI decoupling performance using the partial-element equivalent circuit technique

The design of printed circuit (PC) boards with decoupling capacitors has been the subject of debate and different opinions for many years. The design and electrical impact of the capacitors has been difficult to separate from all other electrical interactions occurring on a conventional PC board populated with integrated circuits. This work demonstrates how the partial-element equivalent circuit (PEEC) modeling technique can be used to accurately predict the performance of various decoupling design strategies. Computer modeling using the PEEC approach is very flexible due to the ease of mixing physical geometries with a large number of circuit elements. Also, the compute time for such practical mixed EM and circuit problems are relatively short. Using this technique, the usual iteration between a number of different designs of test boards can be avoided. We show that the change of the voltage across the PC board, or the voltage gradient, can be used as an effective tool for the improvement of the decoupling efficiency.