Depolarization Field in FeFET Considering Minor Loop Operation and Charge Trapping

The ferroelectric field-effect transistor (FeFET) is a promising candidate for emerging memory. However, data retention loss is a key issue. One reason for the data retention loss is the depolarization field (
${E}_{dep}$
). In this work, we theoretically investigate
${E}_{dep}$
of ferroelectric transistors with the metal/Hf
_0.5
Zr
_0.5
O
₂
/SiO
₂
/Si substrate (MFIS) gate structure considering the minor loop and charge trapping effect at the ferroelectric/interlayer interface. We find that
${E}_{dep}$
increases first and then decreases with the increased interlayer thickness (
${t}_{IL}$
). The charge trapping phenomenon will decrease
${E}_{dep}$
and make
${t}_{IL}$
at which
${E}_{dep}$
reaches the peak value larger. To design a ferroelectric transistor considering both the depolarization field and the memory window, different schemes about how to choose suitable interlayer and ferroelectric layer thicknesses in three different regions need to be adopted.