A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS

This article presents a 12–14.5-GHz fractional-
${N}$
subsampling phase-locked loop (PLL). Due to the subsampling topology, the noise in the subsampling phase detector (SSPD) and the subsampling charge pump (SSCP) is not multiplied by the divider ratio, improving the in-band phase noise. The multiphase generation required for the fractional-
${N}$
operation is implemented by both the digital-to-time-converter (DTC) and the phase interpolator to reduce the total delay required by the DTC, thereby suppressing the DTC intrinsic jitter. The proposed phase interpolator completely cancels out the short-current path by redefining the phase relationship between the input and the reset signal, improving its linearity significantly. The class-C voltage-controlled oscillator (VCO) consumes only 3.2 mW at 13.76 GHz while achieving −106-dBc/Hz phase noise at a 1-MHz offset. Designed and fabricated in 40-nm CMOS technology, the PLL operating in fractional-
${N}$
mode consumes 10.2 mW of power from a 1-V supply. The rms jitter integrated from 1 kHz to 100 MHz is 111 fs, arriving at a figure of merit (FoM) of −249 dB.