Divulge of Root Cause Failure in Individual Cells of 2× nm Technology DDR4 DRAM at Operating Temperature

This article reveals the leakage mechanisms corresponding to the dominant leakage path of individual tail cells in
$2\times $
nm technology double data rate (DDR)4 DRAM at operating temperature. For leakage path determination, activation energy (
${E}_{a}$
) was used as a tool through its extraction by retention time measurement. To get a wide distribution of
${E}_{a}$
, retention testing was performed at the target retention time (10, 15, 20, or 25 s); during this, the number of retentions failed cells were recorded with each temperature. In this experiment, 1.65 e
⁻²
% of the selected bank cells found retention failures. From the total retention failed cells, the selected commonly retention failed cells at the target retention times comprise 1.5 e
⁻³
% of the selected bank cells. From commonly retention failed cells, the distribution of
${E}_{a}$
is analyzed with the retention time at room temperature. This analysis reveals that subthreshold, junction, and gate-induced drain leakage (GIDL) leakage paths dominate in 3.48%, 93.89%, and 2.61% of the total retention failed cells, respectively, at room temperature. Using another experimental approach, retention testing performed at operating temperature on selected 0.07-ppm retention tail cells concludes that GIDL is the dominant leakage path in this device. Correlation between
${E}_{a}$
and retention time measured at operating temperature (40 °C, 60 °C, or 80 °C) explored the leakage mechanisms corresponding to
${E}_{a}$
of the extracted dominant leakage path (GIDL). These failure leakage mechanisms, dominating on certain values of operating temperature, are divulged as the root cause of failure at that temperature.