Design of dual-rate PID controllers

This paper is concerned with the computation of dual-rate high-order-hold PID discrete equivalent controllers. We assume that a continuous-time PID controller has been already designed in order to meet continuous time-domain and/or frequency-domain specifications. Based on the well-known lifting technique, dual-rate high-order-hold circuits and discrete equivalent controllers are proposed. The dual-rate controller is obtained by combining a dual-rate high-order-hold with two single-rate controllers, one at high frequency and the other at low frequency. They are related to the PD and PI action respectively. The effectiveness of the dual-rate sampling can be easily studied a priori at single-rate low frequency (constrained frequency) by analyzing its effects on the system when the ratio between sampling frequencies goes to infinity. An application example is presented.